DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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it) and ModelSim Altera Starter Edition 6.6c software on a PC executing Windows XP Service Pack 3. All tests performed were performed extensively while trying to cover all possible combinations of inputs and outputs for the 1 – Wire® Master. No failures were observed for any of the four tests described below. The source code for all modules, testbench code, and simulation results are located on the DVD included with this work. Table 5.3 shows FPGA resource utilization for the Altera DE2 Development and Education board. Table 5.3 Resource Utilization. Revision Name one_wm Family Cyclone II Device EP2C35F672C6 Timing Models Final Met timing requirements Yes Total logic elements 435 / 33,216 ( 1 % ) Total combinational functions 425 / 33,216 ( 1 % ) Dedicated logic registers 145 / 33,216 ( < 1 % ) Total registers 145 Total pins 20 / 475 ( 4 % ) Total virtual pins 0 Total memory bits 0 / 483,840 ( 0 % ) Embedded Multiplier 9-bit element 0 / 70 ( 0 % ) Total PLLs 0 / 4 ( 0 % ) Each one_wm transaction consists of the following instruction sequence: 1 – Wire® Reset, a device addressing instruction, and a data access instruction. A 1 – Wire® Reset consists of generating a 1 – Wire® Reset/Presence Detect pulse on the 1 – Wire® bus. The state of the 1 – Wire® bus is then sampled and a value of ‘1’ is returned if no Presence Detect pulse was found and a value of ‘0’ is returned otherwise (i.e. slave device(s) found). A device addressing instruction may be one of the following: READ_ROM (0x33), MATCH_ROM (0x55), SKIP_ROM (0xCC), OD_SKIP_ROM (0x3C), or OD_MATCH_ROM (0x69). 131
READ_ROM – Used to read the 64-bit ROM ID directly. It can only be used on a 1 – Wire® network where there is only one device attached. If there are several slave devices connected to the bus, the result of this command will be the <strong>AND</strong> result of all slave device identifiers. Assuming that communication is flawless, the presence of several slaves is indicated by a failed CRC. MATCH_ROM – Used to address individual slave devices on the bus. After this command is issued, the complete 64-bit identifier is transmitted on the bus. When this is done, only the device with exactly this identifier is allowed to answer until the next reset pulse is received. SKIP_ROM – Used when no specific slave is targeted. On a one-slave bus, this command is sufficient for addressing. On a multiple-slave bus, this command can be used to address all devices at once. This is only useful when sending commands to slave devices, e.g. to start temperature conversions on several temperature sensors at once. It is not possible to use the SKIP_ROM command when reading from slave devices on a multiple-slave bus. OD_SKIP_ROM – This command is similar to the SKIP_ROM command but it not only selects devices, it also sets those devices to the Overdrive communication rate. This is most often used to set all capable 1 – Wire® slave devices to Overdrive speed. After the devices are communicating in Overdrive, the ROM IDs can be discovered using the conventional Search Rom sequence. OD_MATCH_ROM – This command is identical to the MATCH_ROM command but it also switches the device to the Overdrive communication speed. 132
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
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Figure 3.9 Structure of the Interfr
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error occurs, an Error Frame is gen
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Table 3.4 Error Flag Output Timing
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3.5.2 Error-Passive A node becomes
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where tNBT is the Nominal Bit Time
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Figure 3.12 Propagation Delay Betwe
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3.6.4 Synchronization t t t t (3.
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opposite value is inserted into the
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many systems, the bus length will b
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CHAPTER 4 THE CHALLENGES OF INTERFA
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In June 2004, Maxim Integrated Prod
Page 105 and 106: Wearable sensor technology is a new
Page 107 and 108: In traditional bus architectures, o
Page 109 and 110: Figure 4.3 Centralized arbiter with
Page 111 and 112: For the initial prototype design pr
Page 113 and 114: the ID of 31 transmits a ‘0’ (d
Page 115 and 116: Recently, a technique has been prop
Page 117 and 118: procedure, then the address claim p
Page 119 and 120: paradigms are prevalent in the desi
Page 121 and 122: systems possess a higher flexibilit
Page 123 and 124: fixed identifier and hence a fixed
Page 125 and 126: 348sm Cm 47 8 smbit 11-bit hea
Page 127 and 128: est-case latency occurs when the bu
Page 129 and 130: to break the 1 - Wire® network int
Page 131 and 132: ow, is most critical for power deli
Page 133 and 134: computations have device-specific p
Page 135 and 136: Table 4.7 Example results with N 2
Page 137 and 138: 4.3.5 Communication Speed Different
Page 139 and 140: anging” a port pin on a microproc
Page 141 and 142: From Figure 5.1, the block I/O pins
Page 143 and 144: 5.2.2 Command Register In addition
Page 145 and 146: specifies the selected bit value to
Page 147 and 148: with i > m. This process is repeate
Page 149 and 150: Figure 5.6 Interrupt Register. OW_
Page 151 and 152: the INTR pin will be pulled high si
Page 153 and 154: master reset occurs. Table 5.2 show
Page 155: EN_FOW: Enable Force One Wire. Sett
Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
Page 165 and 166: TBF - The Transmit Buffer provides
Page 167 and 168: compensate for the propagation dela
Page 169 and 170: Figure 5.15 CAN Module memory map [
Page 171 and 172: ‘0’, fast speed mode will be us
Page 173 and 174: COMP-SEL: Comparator Select. When t
Page 175 and 176: Figure 5.18 CAN Status Register. B
Page 177 and 178: that buffer is given to the CPU and
Page 179 and 180: Acceptance Mask Registers (accepted
Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
Page 185 and 186: The transmit clock (ttxclk) is used
Page 187 and 188: 5.3.13 CAN Module Transmit Buffer I
Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
Page 191 and 192: 5.3.20 CAN Node Overview As stated
Page 193 and 194: Read Digital InputsRead the value o
Page 195 and 196: the clock high time is either 5 µs
Page 197 and 198: Yes Perform A/D Conversion on AN0 W
Page 199 and 200: and GP2 and GP5 as outputs. With th
Page 201 and 202: external INT pin, and then branches
Page 203 and 204: Read MCP2515 Rx Buffer for Digital
Page 205 and 206: When a valid message is received, t
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Table 5.19 Resource Utilization. Re
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For this test, only one CAN node wa
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an Error Frame to be generated. Aft
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messages, acknowledge messages, or
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5.3.21.4 Send Basic Frame Test (sen
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going from one node to 30 nodes (se
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Table 6.1 Resource Utilization. Rev
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6.2.1 Test Verification and Overvie
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has read access to this register. T
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system configuration used for this
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or not depends on the number of rec
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6.4. There are two receiving CAN no
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CHAPTER 7 CONCLUSIONS AND FUTURE WO
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a communication bus reset will occu
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For the synthesizable CAN Controlle
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additional CAN nodes were added to
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Fall-Through Stack A LOW level on t
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In conclusion, the prototype system
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REFERENCES [1] IBM ASIC Products Ap
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[22] “CAN - a brief tutorial for
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[44] Microchip MCP2515 - Stand-Alon
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[67] K. Tindell and A. Burns, “Gu
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[88] “Verilog - A Language Refere
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