DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

it) and ModelSim Altera Starter Edition 6.6c software on a PC executing Windows XP Service
Pack 3. All tests performed were performed extensively while trying to cover all possible
combinations of inputs and outputs for the 1 – Wire® Master. No failures were observed for any
of the four tests described below. The source code for all modules, testbench code, and
simulation results are located on the DVD included with this work. Table 5.3 shows FPGA
resource utilization for the Altera DE2 Development and Education board.
Table 5.3 Resource Utilization.
Revision Name one_wm
Family Cyclone II
Device EP2C35F672C6
Timing Models Final
Met timing requirements Yes
Total logic elements 435 / 33,216 ( 1 % )
Total combinational functions 425 / 33,216 ( 1 % )
Dedicated logic registers 145 / 33,216 ( < 1 % )
Total registers 145
Total pins 20 / 475 ( 4 % )
Total virtual pins 0
Total memory bits 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit element 0 / 70 ( 0 % )
Total PLLs 0 / 4 ( 0 % )
Each one_wm transaction consists of the following instruction sequence: 1 – Wire®
Reset, a device addressing instruction, and a data access instruction. A 1 – Wire® Reset consists
of generating a 1 – Wire® Reset/Presence Detect pulse on the 1 – Wire® bus. The state of the 1
– Wire® bus is then sampled and a value of ‘1’ is returned if no Presence Detect pulse was found
and a value of ‘0’ is returned otherwise (i.e. slave device(s) found).
A device addressing instruction may be one of the following: READ_ROM (0x33),
MATCH_ROM (0x55), SKIP_ROM (0xCC), OD_SKIP_ROM (0x3C), or OD_MATCH_ROM
(0x69).
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