DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

master reset occurs. Table 5.2 shows how to find the proper register value based on the CLK
reference frequency (i.e., if using a 40 MHz CLK reference frequency, write a value of 0x8Eh to
this location).
Table 5.2. Clock Divisor Register Settings for Input Clock Rates.
Min CLK
Frequency
(MHz)
5.2.7 Control Register
Max CLK
Frequency
(MHz)
Divider
Ratio
DIV2
128
DIV1
DIV0
PRE1
PRE0
4.0 < 5.0 4 0 1 0 0 0
5.0 < 6.0 5 0 0 0 1 0
6.0 < 7.0 6 0 0 1 0 1
7.0 < 8.0 7 0 0 0 1 1
8.0 < 10.0 8 0 1 1 0 0
10.0 < 12.0 10 0 0 1 1 0
12.0 < 14.0 12 0 1 0 0 1
14.0 < 16.0 14 0 0 1 1 1
16.0 < 20.0 16 1 0 0 0 0
20.0 < 24.0 20 0 1 0 1 0
24.0 < 28.0 24 0 1 1 0 1
28.0 < 32.0 28 0 1 0 1 1
32.0 < 40.0 32 1 0 1 0 0
40.0 < 48.0 40 0 1 1 1 0
48.0 < 56.0 48 1 0 0 0 1
56.0 < 64.0 56 0 1 1 1 1
64.0 < 80.0 64 1 1 0 0 0
80.0 < 96.0 80 1 0 0 1 0
96.0 < 112.0 96 1 0 1 0 1
112.0 < 128.0 112 1 0 0 1 1
Various 1 – Wire® devices utilize different communication protocols in order to properly
function and report back to the master in an efficient manner. The Control Register, shown in
Figure 5.9, adds the robustness needed to handle all of the major conditions expected from each
iButton and 1 – Wire® chip family device.