DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
EN Enable: When EN is low, the 1 – Wire® Master is enabled; this signal acts as the device chip enable. This enables communication between the 1 – Wire® Master and the CPU. INTR Interrupt: This line goes to its active state whenever any one of the interrupt types has an active high condition and is enabled via the Interrupt Enable Register. The INTR signal is reset to an inactive state when the Interrupt Register is read. MRMaster Reset: When this input is high, it clears all the registers and the control logic of the 1 – Wire® Master, and sets INTR to its default inactive state, which is HIGH. RD Read: This pin drives the bus during a read cycle. When the circuit is enabled, the CPU can read status information or data from the selected register by driving RD low. RD and WR should never be low simultaneously; if they are WR takes precedence. STPZ Strong Pull-up Enable: This pin drives the gate of the p-channel transistor that bypasses the weak pull-up resistor in order to provide the slave device with a strong power supply for high current applications. WR Write: This pin drives the bus during a write cycle. When WR is low while the circuit is enabled, the CPU can write control words or data into the selected register. RD and WR should never be low simultaneously; if they are WR takes precedence. 117
5.2.2 Command Register In addition to reading and writing the 1 – Wire® Master can generate two special commands on the bus. The first is a 1 – Wire® reset, which must precede any command given on the 1 – Wire® bus. Secondly, the 1 – Wire® Master can be placed into Search ROM Accelerator mode to prevent the host from having to perform single bit manipulations of the bus during a Search ROM operation (command 0xF0h). For more details on the Reset or Search ROM command, the reader is referred to [75]. In addition to these two functions, the Command Register contains two bits to bypass the 1 – Wire® Master features and control the 1 – Wire® bus directly (See Figure 5.2). Figure 5.2 Command Register Bits. Bit 3 – OW_IN: OW Input. This bit always reflects the current state of the 1 – Wire® line. Bit 2 – FOW: Force One Wire. This bit can be used to bypass 1 – Wire® Master operations and drive the bus directly if needed. Setting this bit high will drive the bus low until it is cleared or a bus reset occurs. While the 1 – Wire® bus is held low, no other 1 – Wire® Master operations will function. By controlling the length of time this bit is set and the point when the line is sampled, any 1 – Wire® communication can be generated by the host controller. To prevent accidental writes to the bus, the EN bit in the CONTROL register must be set to a 1 before the FOW bit will function. The FOW bit is cleared to a 0 on a power-up or master reset. 118
- Page 91 and 92: where tNBT is the Nominal Bit Time
- Page 93 and 94: Figure 3.12 Propagation Delay Betwe
- Page 95 and 96: 3.6.4 Synchronization t t t t (3.
- Page 97 and 98: opposite value is inserted into the
- Page 99 and 100: many systems, the bus length will b
- Page 101 and 102: CHAPTER 4 THE CHALLENGES OF INTERFA
- Page 103 and 104: In June 2004, Maxim Integrated Prod
- Page 105 and 106: Wearable sensor technology is a new
- Page 107 and 108: In traditional bus architectures, o
- Page 109 and 110: Figure 4.3 Centralized arbiter with
- Page 111 and 112: For the initial prototype design pr
- Page 113 and 114: the ID of 31 transmits a ‘0’ (d
- Page 115 and 116: Recently, a technique has been prop
- Page 117 and 118: procedure, then the address claim p
- Page 119 and 120: paradigms are prevalent in the desi
- Page 121 and 122: systems possess a higher flexibilit
- Page 123 and 124: fixed identifier and hence a fixed
- Page 125 and 126: 348sm Cm 47 8 smbit 11-bit hea
- Page 127 and 128: est-case latency occurs when the bu
- Page 129 and 130: to break the 1 - Wire® network int
- Page 131 and 132: ow, is most critical for power deli
- Page 133 and 134: computations have device-specific p
- Page 135 and 136: Table 4.7 Example results with N 2
- Page 137 and 138: 4.3.5 Communication Speed Different
- Page 139 and 140: anging” a port pin on a microproc
- Page 141: From Figure 5.1, the block I/O pins
- Page 145 and 146: specifies the selected bit value to
- Page 147 and 148: with i > m. This process is repeate
- Page 149 and 150: Figure 5.6 Interrupt Register. OW_
- Page 151 and 152: the INTR pin will be pulled high si
- Page 153 and 154: master reset occurs. Table 5.2 show
- Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
- Page 157 and 158: READ_ROM - Used to read the 64-bit
- Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
- Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
- Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
- Page 165 and 166: TBF - The Transmit Buffer provides
- Page 167 and 168: compensate for the propagation dela
- Page 169 and 170: Figure 5.15 CAN Module memory map [
- Page 171 and 172: ‘0’, fast speed mode will be us
- Page 173 and 174: COMP-SEL: Comparator Select. When t
- Page 175 and 176: Figure 5.18 CAN Status Register. B
- Page 177 and 178: that buffer is given to the CPU and
- Page 179 and 180: Acceptance Mask Registers (accepted
- Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
- Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
- Page 185 and 186: The transmit clock (ttxclk) is used
- Page 187 and 188: 5.3.13 CAN Module Transmit Buffer I
- Page 189 and 190: Figure 5.28 CAN Transmit Data Segme
- Page 191 and 192: 5.3.20 CAN Node Overview As stated
EN Enable: When EN is low, the 1 – Wire® Master is enabled; this signal acts as<br />
the device chip enable. This enables communication between the 1 – Wire® Master and<br />
the CPU.<br />
INTR Interrupt: This line goes to its active state whenever any one of the interrupt<br />
types has an active high condition and is enabled via the Interrupt Enable Register. The<br />
INTR signal is reset to an inactive state when the Interrupt Register is read.<br />
MRMaster Reset: When this input is high, it clears all the registers and the control<br />
logic of the 1 – Wire® Master, and sets INTR to its default inactive state, which is HIGH.<br />
RD Read: This pin drives the bus during a read cycle. When the circuit is enabled,<br />
the CPU can read status information or data from the selected register by driving RD<br />
low. RD and WR should never be low simultaneously; if they are WR takes<br />
precedence.<br />
STPZ Strong Pull-up Enable: This pin drives the gate of the p-channel transistor that<br />
bypasses the weak pull-up resistor in order to provide the slave device with a strong<br />
power supply for high current applications.<br />
WR Write: This pin drives the bus during a write cycle. When WR is low while<br />
the circuit is enabled, the CPU can write control words or data into the selected register.<br />
RD and WR should never be low simultaneously; if they are WR takes<br />
precedence.<br />
117
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