DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

anging” a port pin on a microprocessor, and having the microprocessor perform the timing
functions required for the 1 – Wire® protocol. Even though 1 – Wire® transmissions can be
interrupted mid-byte, they cannot be interrupted during the “low” time of a bit time slot; this
means that a CPU will be idle for up to 60 microseconds for each bit sent and at least 480
microseconds when performing a 1 – Wire® reset [75].
5.2.1 1 – Wire® Master Overview
The synthesizable 1 – Wire® Master implemented here, termed one_wm, was created to
facilitate host CPU communication with devices over a 1 – Wire® bus without concern for bit
timing and without tying up valuable CPU cycles. Some of the features incorporated into the
design include:
Support for long line conditions.
Support for single bit transmissions.
Memory maps into any standard byte-wide data bus.
Search ROM accelerator relieves the CPU from any single bit operations on the 1 –
Wire® bus.
Generates interrupts to provide for more efficient programming.
Eliminates CPU “bit-banging” by internally generating all 1 – Wire® timing and control
signals.
Supports standard and overdrive communication speeds.
Capable of running off any system clock from 4 MHz up to 128 MHz.
Supports strong pull-up specifications as defined by the 1 – Wire® protocol standards.
114