DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

CHAPTER 5
THE INTERFACE OF CAN AND 1 – WIRE® COMMUNICATION PROTOCOLS
5.1 Interface Overview
In many situations, especially those involving cutting-edge technology, new designs have
unanticipated problems that are difficult to predict by modeling or simulations. When the
performance of a new device is uncertain, an early development of a prototype can be useful for
testing the key features of the design, exploring design alternatives, testing theories, and
confirming performance prior to starting production [74]. Since prototyping is an iterative
process, a series of products will be designed, constructed, and tested to refine the final design.
The prototype design presented here consists of a 1 – Wire® Bus Master and a CAN
Transceiver. Both components in the prototype system have been designed in Verilog®, so they
can be targeted to different implementation technologies. To implement all of the prototype
design components, the DE2 Development and Education Board, equipped with a Cyclone II
(2C35) FPGA, manufactured by Altera was used for all design synthesis and simulations.
5.2 1 – Wire® FPGA Implementation
As more 1 – Wire® devices become available, more and more users have to deal with the
demands of generating 1 – Wire® signals to communicate to them. This usually requires “bit-
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