DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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The recovery time is longest for low operating voltage and low temperature. If the application requires operation at very low temperatures, the -40°C entry should be used. For room-temperature environments, it is acceptable to use the +25°C entry, which also allows safe operation at higher temperatures. The +85°C entry yields a result that only applies at that temperature; it should be regarded as a reference, not as a design value for other temperatures. The recovery is shortest for high operating voltages. The 4.5V entries apply for pullup voltages of 4.5V or higher. A recovery time based on 2.8V entries also works for higher voltages, but unnecessarily slows the data rate. For an operating voltage, say Vx, between 2.8V and 4.5V, a new slope value can be obtained through linear interpolation using equation 4.9 [72]. Slope@2.8V Vx 2.8V Slope@Vx Slope@2.8V Slope@4.5V (4.9) 1.7V As a second example, assume that an application requires a network of twenty 1 – Wire® devices N 20 , with tW0L = 60µs at standard speed and 6µs at overdrive (from DS2411 data sheet). The network is supposed to operate from 0°C to 70°C. The operating voltage is not unknown. The applicable entry for this temperature range is that of -5°C, because it is the nearest value below the minimum operating temperature. Since the slope for higher temperatures is lower than that of the -5°C entry, the result is valid for all temperatures above - 5°C. Table 4.7 shows the tREC results for this example and the maximum data rate with this recovery time. 109
Table 4.7 Example results with N 20 . Operating Voltage (V) Standard Speed Overdrive Speed t 1.99 N 1.0 s t 1.37 N 0.5 s 4.5 and higher 2.8 (minimum) REC data rate REC 1.99 20 1.0 40.8s data rate 1 t t W 0L REC 1 60s40.8s 9.92 kbps 3.30 1.0 3.30 20 1.0 1 t t W 0L REC 1 60s67s 7.87 kbps 110 s t N s 67s s REC data rate REC 1.37 20 0.5 27.9s data rate 1 t t W 0L REC 1 6s27.9s 29.5 kbps 1.80 0.5 1.80 20 0.5 1 t t W 0L REC 1 6s36.5s 23.5 kbps s t N s 36.5s At standard speed, the data rate is reduced to approximately 65% of the 15.3 kbps for an operating voltage of 4.5V and is reduced to approximately 51% when the minimum 2.8V operating voltage is used. At overdrive speed, the data rate is less than 25% of the 125 kbps reference for operating voltages of 4.5V and higher. When operating at the minimum operating voltage of 2.8V, the data rate is less than 20% of the 125 kbps reference. If any of the data rates in Table 4.7 is acceptable for the application, the choice of operating voltage is not critical. However, if an operating voltage of approximately 5V is available, it should be preferred because of better noise immunity. s
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
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2.4.2 Device Functions and Typical
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and development (R&D) investments b
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2.5 Network Types and Precedents As
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2.5.2 1 - Wire® Network Topologies
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2.5.3 1 - Wire® Network Limitation
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with a single selected slave. If an
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user group was founded in March of
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protocol on multiple media for maxi
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ecessive bit and the monitored stat
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specification: Start-Of-Frame, Arbi
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Cyclic Redundancy Check (CRC) Field
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Arbitration FieldThe Arbitration Fi
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SOF SOF Bit 28 Bit 27 Arbitration f
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Afterwards it starts transmitting s
Page 83 and 84: Figure 3.9 Structure of the Interfr
Page 85 and 86: error occurs, an Error Frame is gen
Page 87 and 88: Table 3.4 Error Flag Output Timing
Page 89 and 90: 3.5.2 Error-Passive A node becomes
Page 91 and 92: where tNBT is the Nominal Bit Time
Page 93 and 94: Figure 3.12 Propagation Delay Betwe
Page 95 and 96: 3.6.4 Synchronization t t t t (3.
Page 97 and 98: opposite value is inserted into the
Page 99 and 100: many systems, the bus length will b
Page 101 and 102: CHAPTER 4 THE CHALLENGES OF INTERFA
Page 103 and 104: In June 2004, Maxim Integrated Prod
Page 105 and 106: Wearable sensor technology is a new
Page 107 and 108: In traditional bus architectures, o
Page 109 and 110: Figure 4.3 Centralized arbiter with
Page 111 and 112: For the initial prototype design pr
Page 113 and 114: the ID of 31 transmits a ‘0’ (d
Page 115 and 116: Recently, a technique has been prop
Page 117 and 118: procedure, then the address claim p
Page 119 and 120: paradigms are prevalent in the desi
Page 121 and 122: systems possess a higher flexibilit
Page 123 and 124: fixed identifier and hence a fixed
Page 125 and 126: 348sm Cm 47 8 smbit 11-bit hea
Page 127 and 128: est-case latency occurs when the bu
Page 129 and 130: to break the 1 - Wire® network int
Page 131 and 132: ow, is most critical for power deli
Page 133: computations have device-specific p
Page 137 and 138: 4.3.5 Communication Speed Different
Page 139 and 140: anging” a port pin on a microproc
Page 141 and 142: From Figure 5.1, the block I/O pins
Page 143 and 144: 5.2.2 Command Register In addition
Page 145 and 146: specifies the selected bit value to
Page 147 and 148: with i > m. This process is repeate
Page 149 and 150: Figure 5.6 Interrupt Register. OW_
Page 151 and 152: the INTR pin will be pulled high si
Page 153 and 154: master reset occurs. Table 5.2 show
Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
Page 157 and 158: READ_ROM - Used to read the 64-bit
Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
Page 165 and 166: TBF - The Transmit Buffer provides
Page 167 and 168: compensate for the propagation dela
Page 169 and 170: Figure 5.15 CAN Module memory map [
Page 171 and 172: ‘0’, fast speed mode will be us
Page 173 and 174: COMP-SEL: Comparator Select. When t
Page 175 and 176: Figure 5.18 CAN Status Register. B
Page 177 and 178: that buffer is given to the CPU and
Page 179 and 180: Acceptance Mask Registers (accepted
Page 181 and 182: SJW1, SJW0: Synchronization Jump Wi
Page 183 and 184: TSEG22 - TSEG10: Time Segment Bits.
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The transmit clock (ttxclk) is used
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5.3.13 CAN Module Transmit Buffer I
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Figure 5.28 CAN Transmit Data Segme
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5.3.20 CAN Node Overview As stated
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Read Digital InputsRead the value o
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the clock high time is either 5 µs
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Yes Perform A/D Conversion on AN0 W
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and GP2 and GP5 as outputs. With th
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external INT pin, and then branches
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Read MCP2515 Rx Buffer for Digital
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When a valid message is received, t
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Table 5.19 Resource Utilization. Re
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For this test, only one CAN node wa
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an Error Frame to be generated. Aft
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messages, acknowledge messages, or
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5.3.21.4 Send Basic Frame Test (sen
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going from one node to 30 nodes (se
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Table 6.1 Resource Utilization. Rev
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6.2.1 Test Verification and Overvie
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has read access to this register. T
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system configuration used for this
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or not depends on the number of rec
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6.4. There are two receiving CAN no
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CHAPTER 7 CONCLUSIONS AND FUTURE WO
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a communication bus reset will occu
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For the synthesizable CAN Controlle
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additional CAN nodes were added to
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Fall-Through Stack A LOW level on t
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In conclusion, the prototype system
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REFERENCES [1] IBM ASIC Products Ap
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[22] “CAN - a brief tutorial for
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[44] Microchip MCP2515 - Stand-Alon
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[67] K. Tindell and A. Burns, “Gu
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[88] “Verilog - A Language Refere
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