DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
300µs, leaving 180µs for tREC. At overdrive speed, these numbers are ten times shorter, reducing tREC to 18µs. Compared to the minimum data sheet specification of tREC, plenty of time remains for the parasitic power supply (a capacitor inside the slave) to recharge. Therefore, the reset/presence detect cycle is not critical for power considerations, as long as tRSTL does not exceed the data sheet’s maximum limit and the parasitic power supply is sufficiently charged before tRSTL begins. At overdrive speed an extended recovery time of 2.5 times the minimum value prior to a reset pulse provides this extra charge. At standard speed the extended recovery time prior to a reset pulse is optional. Figure 4.9 Initialization Procedure: Reset and Presence Pulse [72 – 73]. The read/write timing diagram below consists of three waveforms: Write-One Time Slot- to write a logical ‘1’ (Figure 4.10); Write Zero Time Slot-to write a logical ‘0’ (Figure 4.11); and Read Data Time Slot-to read a bit from a 1 – Wire® slave (Figure 4.12). As can easily be seen from Figure 4.10, a Write-One Time Slot is not critical for power delivery. The window for power delivery, tSLOT – tW1L (Write-one low time), is at least 50µs at standard speed and 6µs at overdrive speed. The 6µs at overdrive speed, however, are barely more than the minimum specification of tREC. The Write-Zero Time Slot, especially when there are multiple zeros in a 105
ow, is most critical for power delivery due to the long low-time compared to the recovery time. It is important to understand that the tREC specification in the product data sheets for 1 – Wire® devices applies for a single slave on a 1 – Wire® line with a 2.2kΩ pullup resistor to 2.8V. A Read-Data Time Slot, when reading a zero, is also critical for power delivery. It is, however, more benign since a slave typically pulls the 1 – Wire® line low for less than the permissible 60µs (standard speed) or 6µs (overdrive speed). Figure 4.10 Write-One Time Slot [72 – 73]. Figure 4.11 Write-Zero Time Slot [72 – 73]. 106
- Page 79 and 80: SOF SOF Bit 28 Bit 27 Arbitration f
- Page 81 and 82: Afterwards it starts transmitting s
- Page 83 and 84: Figure 3.9 Structure of the Interfr
- Page 85 and 86: error occurs, an Error Frame is gen
- Page 87 and 88: Table 3.4 Error Flag Output Timing
- Page 89 and 90: 3.5.2 Error-Passive A node becomes
- Page 91 and 92: where tNBT is the Nominal Bit Time
- Page 93 and 94: Figure 3.12 Propagation Delay Betwe
- Page 95 and 96: 3.6.4 Synchronization t t t t (3.
- Page 97 and 98: opposite value is inserted into the
- Page 99 and 100: many systems, the bus length will b
- Page 101 and 102: CHAPTER 4 THE CHALLENGES OF INTERFA
- Page 103 and 104: In June 2004, Maxim Integrated Prod
- Page 105 and 106: Wearable sensor technology is a new
- Page 107 and 108: In traditional bus architectures, o
- Page 109 and 110: Figure 4.3 Centralized arbiter with
- Page 111 and 112: For the initial prototype design pr
- Page 113 and 114: the ID of 31 transmits a ‘0’ (d
- Page 115 and 116: Recently, a technique has been prop
- Page 117 and 118: procedure, then the address claim p
- Page 119 and 120: paradigms are prevalent in the desi
- Page 121 and 122: systems possess a higher flexibilit
- Page 123 and 124: fixed identifier and hence a fixed
- Page 125 and 126: 348sm Cm 47 8 smbit 11-bit hea
- Page 127 and 128: est-case latency occurs when the bu
- Page 129: to break the 1 - Wire® network int
- Page 133 and 134: computations have device-specific p
- Page 135 and 136: Table 4.7 Example results with N 2
- Page 137 and 138: 4.3.5 Communication Speed Different
- Page 139 and 140: anging” a port pin on a microproc
- Page 141 and 142: From Figure 5.1, the block I/O pins
- Page 143 and 144: 5.2.2 Command Register In addition
- Page 145 and 146: specifies the selected bit value to
- Page 147 and 148: with i > m. This process is repeate
- Page 149 and 150: Figure 5.6 Interrupt Register. OW_
- Page 151 and 152: the INTR pin will be pulled high si
- Page 153 and 154: master reset occurs. Table 5.2 show
- Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
- Page 157 and 158: READ_ROM - Used to read the 64-bit
- Page 159 and 160: 5.2.8.1 Single Search ROM (single_s
- Page 161 and 162: 5.2.8.3 Scratchpad Memory (scratchp
- Page 163 and 164: 5.2.8.4 Command Recognition (cmd_re
- Page 165 and 166: TBF - The Transmit Buffer provides
- Page 167 and 168: compensate for the propagation dela
- Page 169 and 170: Figure 5.15 CAN Module memory map [
- Page 171 and 172: ‘0’, fast speed mode will be us
- Page 173 and 174: COMP-SEL: Comparator Select. When t
- Page 175 and 176: Figure 5.18 CAN Status Register. B
- Page 177 and 178: that buffer is given to the CPU and
- Page 179 and 180: Acceptance Mask Registers (accepted
ow, is most critical for power delivery due to the long low-time compared to the recovery time.<br />
It is important to understand that the tREC specification in the product data sheets for 1 – Wire®<br />
devices applies for a single slave on a 1 – Wire® line with a 2.2kΩ pullup resistor to 2.8V. A<br />
Read-Data Time Slot, when reading a zero, is also critical for power delivery. It is, however,<br />
more benign since a slave typically pulls the 1 – Wire® line low for less than the permissible<br />
60µs (standard speed) or 6µs (overdrive speed).<br />
Figure 4.10 Write-One Time Slot [72 – 73].<br />
Figure 4.11 Write-Zero Time Slot [72 – 73].<br />
106
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