DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

time-triggered architectures help in managing the complexity of fault-tolerance and
corresponding formal dependability models, as required for the establishment of ultra-high
reliability (failure rates in the order of 10 -9 failures/hour) [51]. The predetermined points in time
of periodic message transmissions allow error detection and redundancy to be integrated
transparently into applications without any modification of the function and timing of the system.
A time-triggered system also supports replica determinism, which is essential for establishing
fault-tolerance through active redundancy. The communication controller in a time-triggered
system decides autonomously when a message is transmitted.
One drawback, however, of time-triggered bus concepts is the lack of flexibility and the
restrictive design process. All processes and their time specifications must be known in advance.
Otherwise, an efficient implementation is not possible. Furthermore, the communication and the
task scheduling on the control units have to be synchronized during operation in order to ensure
the strict timing specifications of the system design [57].
In non safety-critical (soft real-time) applications, however, the event-triggered control
paradigm may be preferred due to higher flexibility and resource efficiency. Event-triggered
architectures support dynamic resource allocation strategies and resource sharing. In event-
triggered systems, the provision of resources can be biased towards average demands, thus
allowing timing failures to occur during worst-case scenarios in favor of more cost-effective
solutions [58]. The main advantage of event-triggered systems is their ability to quickly react to
asynchronous external events which are not known in advance [59]. Thus, they show a better
real-time performance in comparison with time-triggered systems. In addition, event-triggered
95