DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

In traditional bus architectures, one or more bus masters and bus slaves connect to a
shared bus, and when multiple masters attempt to access the bus at the same time, the arbiter
allocates the bus resources to a single master, forcing all other masters to wait. One shortcoming
of this method is that access to the shared system bus becomes the bottleneck for data
throughput. Since only one master has access to the bus at a time, this means that other masters
are forced to wait and only one slave can transfer data at a time [37].
In centralized arbitration schemes, a single arbiter is used to select the next master. A
simple form of centralized arbitration uses a bus request line, a bus grant line, and a bus busy
line. Each of these lines is shared by potential masters, which are daisy-chained in a cascade as
shown in Figure 4.1 [38].
Figure 4.1 Centralized arbiter in a daisy-chain scheme [38].
In Figure 4.1, each of the potential masters can submit a bus request at any time. A fixed
priority is set among the masters from left to right. When a bus request is received at the central
bus arbiter, it issues a bus grant by asserting the bus grant line. When the potential master that is
closest to the arbiter (Potential Master 1) sees the bus grant signal, it checks to see if it had made
a bus request. If yes, it takes over the bus and stops propagation of the bus grant signal any
further [38]. If it has not made a request, it will simply pass the bus grant signal to the next
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