DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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triggered and time-triggered control paradigms, timing performance in relation to potential latencies, and possible communication speed differences. 4.3.1 Multi-Master to Single Master Bridging a multi-master and a single-master communication protocol might seem a bit daunting at first to a systems design engineer. However, communication protocols supporting more than one master have an arbitration scheme in place that is either controlled in hardware or by software. Examples of communication protocols that contain provisions for multiple masters include: I 2 C, SPI [33 – 35], and CAN. Communication protocols such as Local Interconnect Network (LIN), 1 – Wire®, and Joint Test Action Group (JTAG) support only a single master and therefore need no arbitrator or bus arbitration scheme to help with communication conflicts. Bus arbitration provides a method for resolving bus control conflicts and assigning priorities to the requests for control of the bus. It is needed to resolve conflicts when two or more devices want to become the bus master at the same time. In short, arbitration is the process of selecting the next bus master from among multiple candidates. Traditionally, a single arbitrator schedules communication between one or more bus masters and bus slaves. If multiple masters attempt to access the bus, the arbitrator allocates bus resources to a single master based on a fixed set of arbitration rules [36]. Although there are many different types of arbitration schemes employed in both hardware and software, conflicts can be resolved based on fairness or priority in centralized or distributed mechanisms. 81
In traditional bus architectures, one or more bus masters and bus slaves connect to a shared bus, and when multiple masters attempt to access the bus at the same time, the arbiter allocates the bus resources to a single master, forcing all other masters to wait. One shortcoming of this method is that access to the shared system bus becomes the bottleneck for data throughput. Since only one master has access to the bus at a time, this means that other masters are forced to wait and only one slave can transfer data at a time [37]. In centralized arbitration schemes, a single arbiter is used to select the next master. A simple form of centralized arbitration uses a bus request line, a bus grant line, and a bus busy line. Each of these lines is shared by potential masters, which are daisy-chained in a cascade as shown in Figure 4.1 [38]. Figure 4.1 Centralized arbiter in a daisy-chain scheme [38]. In Figure 4.1, each of the potential masters can submit a bus request at any time. A fixed priority is set among the masters from left to right. When a bus request is received at the central bus arbiter, it issues a bus grant by asserting the bus grant line. When the potential master that is closest to the arbiter (Potential Master 1) sees the bus grant signal, it checks to see if it had made a bus request. If yes, it takes over the bus and stops propagation of the bus grant signal any further [38]. If it has not made a request, it will simply pass the bus grant signal to the next 82
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
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in Figure 2.15. Alternatively, the
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of the bit, then write the desired
Page 55 and 56: 2.4.2 Device Functions and Typical
Page 57 and 58: and development (R&D) investments b
Page 59 and 60: 2.5 Network Types and Precedents As
Page 61 and 62: 2.5.2 1 - Wire® Network Topologies
Page 63 and 64: 2.5.3 1 - Wire® Network Limitation
Page 65 and 66: with a single selected slave. If an
Page 67 and 68: user group was founded in March of
Page 69 and 70: protocol on multiple media for maxi
Page 71 and 72: ecessive bit and the monitored stat
Page 73 and 74: specification: Start-Of-Frame, Arbi
Page 75 and 76: Cyclic Redundancy Check (CRC) Field
Page 77 and 78: Arbitration FieldThe Arbitration Fi
Page 79 and 80: SOF SOF Bit 28 Bit 27 Arbitration f
Page 81 and 82: Afterwards it starts transmitting s
Page 83 and 84: Figure 3.9 Structure of the Interfr
Page 85 and 86: error occurs, an Error Frame is gen
Page 87 and 88: Table 3.4 Error Flag Output Timing
Page 89 and 90: 3.5.2 Error-Passive A node becomes
Page 91 and 92: where tNBT is the Nominal Bit Time
Page 93 and 94: Figure 3.12 Propagation Delay Betwe
Page 95 and 96: 3.6.4 Synchronization t t t t (3.
Page 97 and 98: opposite value is inserted into the
Page 99 and 100: many systems, the bus length will b
Page 101 and 102: CHAPTER 4 THE CHALLENGES OF INTERFA
Page 103 and 104: In June 2004, Maxim Integrated Prod
Page 105: Wearable sensor technology is a new
Page 109 and 110: Figure 4.3 Centralized arbiter with
Page 111 and 112: For the initial prototype design pr
Page 113 and 114: the ID of 31 transmits a ‘0’ (d
Page 115 and 116: Recently, a technique has been prop
Page 117 and 118: procedure, then the address claim p
Page 119 and 120: paradigms are prevalent in the desi
Page 121 and 122: systems possess a higher flexibilit
Page 123 and 124: fixed identifier and hence a fixed
Page 125 and 126: 348sm Cm 47 8 smbit 11-bit hea
Page 127 and 128: est-case latency occurs when the bu
Page 129 and 130: to break the 1 - Wire® network int
Page 131 and 132: ow, is most critical for power deli
Page 133 and 134: computations have device-specific p
Page 135 and 136: Table 4.7 Example results with N 2
Page 137 and 138: 4.3.5 Communication Speed Different
Page 139 and 140: anging” a port pin on a microproc
Page 141 and 142: From Figure 5.1, the block I/O pins
Page 143 and 144: 5.2.2 Command Register In addition
Page 145 and 146: specifies the selected bit value to
Page 147 and 148: with i > m. This process is repeate
Page 149 and 150: Figure 5.6 Interrupt Register. OW_
Page 151 and 152: the INTR pin will be pulled high si
Page 153 and 154: master reset occurs. Table 5.2 show
Page 155 and 156: EN_FOW: Enable Force One Wire. Sett
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READ_ROM - Used to read the 64-bit
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5.2.8.1 Single Search ROM (single_s
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5.2.8.3 Scratchpad Memory (scratchp
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5.2.8.4 Command Recognition (cmd_re
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TBF - The Transmit Buffer provides
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compensate for the propagation dela
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Figure 5.15 CAN Module memory map [
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‘0’, fast speed mode will be us
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COMP-SEL: Comparator Select. When t
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Figure 5.18 CAN Status Register. B
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that buffer is given to the CPU and
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Acceptance Mask Registers (accepted
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SJW1, SJW0: Synchronization Jump Wi
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TSEG22 - TSEG10: Time Segment Bits.
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The transmit clock (ttxclk) is used
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5.3.13 CAN Module Transmit Buffer I
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Figure 5.28 CAN Transmit Data Segme
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5.3.20 CAN Node Overview As stated
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Read Digital InputsRead the value o
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the clock high time is either 5 µs
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Yes Perform A/D Conversion on AN0 W
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and GP2 and GP5 as outputs. With th
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external INT pin, and then branches
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Read MCP2515 Rx Buffer for Digital
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When a valid message is received, t
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Table 5.19 Resource Utilization. Re
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For this test, only one CAN node wa
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an Error Frame to be generated. Aft
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messages, acknowledge messages, or
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5.3.21.4 Send Basic Frame Test (sen
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going from one node to 30 nodes (se
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Table 6.1 Resource Utilization. Rev
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6.2.1 Test Verification and Overvie
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has read access to this register. T
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system configuration used for this
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or not depends on the number of rec
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6.4. There are two receiving CAN no
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CHAPTER 7 CONCLUSIONS AND FUTURE WO
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a communication bus reset will occu
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For the synthesizable CAN Controlle
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additional CAN nodes were added to
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Fall-Through Stack A LOW level on t
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In conclusion, the prototype system
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REFERENCES [1] IBM ASIC Products Ap
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[22] “CAN - a brief tutorial for
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[44] Microchip MCP2515 - Stand-Alon
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[67] K. Tindell and A. Burns, “Gu
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[88] “Verilog - A Language Refere
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