DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...

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Identification and Authentication and Accessory/Peripheral Identification and Control (See Section 2.4.2 for more details). Again, combining CAN and 1 – Wire® would increase the features and functionality of the overall system. Although CAN is the dominant serial communication protocol preferred in the automotive industry, 1 – Wire® devices are gaining popularity, especially with the emergence of hybrid and all-electric vehicles and technologies. As the result of new developments on experimental battery-powered electric vehicles, the need for fast information related to different components and equipment emerges, especially data related to battery life and knowledge about the overall system efficiency [30]. Battery monitoring systems for electric vehicles is one of the biggest uses of 1 – Wire® devices in the automotive industry. Most applications use the DS2436, a battery ID and monitor chip, to allow voltage and temperature monitoring of all batteries. This allows early detection of problems or failures in individual batteries. Another application of iButtons in the automotive industry is the vehicle black box. Like that found in commercial airliners, the Road Safety On-Board Computer System is a new car device that monitors speed, braking, turns, and just about everything else. It is designed to show you just what kind of driver you are. Before the engine will start, you have to log on with an iButton that tells the car who you are and from that point on, every move you make is strictly on the record. Combining the simplicity of CAN-enabling a device and application-specific 1 – Wire® devices such as the DS2436 and other function-specific 1 – Wire® devices, a system designer will be able to design a reliable, rugged, and functionally diverse network for almost any application. 77
In June 2004, Maxim Integrated Products introduced the DS2482-X00 I 2 C-to-1 – Wire® interface devices, bridging a multi-master communication protocol with a single master communication protocol. The DS2482-X00 is an I 2 C-to-1 – Wire® line driver with one (DS2482-100) or eight (DS2482-800) channels of independently operated 1 – Wire® I/O ports. The DS2482 is an I 2 C-to-1 – Wire® bridge device that interfaces directly to standard (100 kHz max) or fast (400 kHz max) I 2 C masters to perform bidirectional protocol conversion between the I 2 C master and any downstream 1 – Wire® slave devices. Relative to any attached 1 – Wire® slave device, the DS2482 is a 1 – Wire® Master. I 2 C is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed. Some common applications include: reading hardware monitors and diagnostic sensors, like a CPU thermostat and fan speed; reading real-time clocks; and turning on and turning off the power supply of system components. Peripherals can also be added or removed from the I 2 C bus while the system is running, just like 1 – Wire® devices, which makes it ideal for applications that require hot swapping of components [13 – 15]. Combining the diverse functionality of 1 – Wire® devices with the simplicity and low manufacturing cost of I 2 C, reduces the wiring complexity of any system down to just two wires and gives the system designer greater application diversity. 4.2 Applications Of the many commercial markets that could potentially benefit from the interfacing of CAN and 1 – Wire® technologies, two of the most rapidly emerging markets, wearable sensor technology and automotive electronics and sensors would benefit the most. Other applications and markets that could benefit include hybrid mining and construction equipment, mobile and 78
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DESIGN OF A CUSTOM ASIC INCORPORATI
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ABSTRACT The vast majority of today
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LIST OF ABBREVIATIONS AND SYMBOLS A
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ISO International Organization for
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SI Serial In SO Serial Out SOF Star
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ACKNOWLEDGEMENTS I would like to ex
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2.4 Types of Devices...............
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4.3.5 Communication Speed Different
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5.3.21.1 Synchronization Test (test
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5.3 Resource Utilization...........
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LIST OF FIGURES 2.1 1 - Wire® Netw
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4.12 Read-Data Time Slot...........
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6.4 DS1996 Address Registers ......
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manufacturing process. Structured o
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describes the 1 - Wire® and CAN co
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2.2 1 - Wire® Overview The basis o
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All 1 - Wire® masters described in
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attachments, microcontroller with b
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Figure 2.3 Bidirectional port pin w
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2.3.3 Synthesizable 1 - Wire® Bus
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Figure 2.7 UART/RS232 Serial Port I
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hardware. Through control registers
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Table 2.2 1 - Wire® Bus Operations
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2.3.6 1 - Wire® Search Algorithm F
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detected. This ‘read two bits’
Page 51 and 52: in Figure 2.15. Alternatively, the
Page 53 and 54: of the bit, then write the desired
Page 55 and 56: 2.4.2 Device Functions and Typical
Page 57 and 58: and development (R&D) investments b
Page 59 and 60: 2.5 Network Types and Precedents As
Page 61 and 62: 2.5.2 1 - Wire® Network Topologies
Page 63 and 64: 2.5.3 1 - Wire® Network Limitation
Page 65 and 66: with a single selected slave. If an
Page 67 and 68: user group was founded in March of
Page 69 and 70: protocol on multiple media for maxi
Page 71 and 72: ecessive bit and the monitored stat
Page 73 and 74: specification: Start-Of-Frame, Arbi
Page 75 and 76: Cyclic Redundancy Check (CRC) Field
Page 77 and 78: Arbitration FieldThe Arbitration Fi
Page 79 and 80: SOF SOF Bit 28 Bit 27 Arbitration f
Page 81 and 82: Afterwards it starts transmitting s
Page 83 and 84: Figure 3.9 Structure of the Interfr
Page 85 and 86: error occurs, an Error Frame is gen
Page 87 and 88: Table 3.4 Error Flag Output Timing
Page 89 and 90: 3.5.2 Error-Passive A node becomes
Page 91 and 92: where tNBT is the Nominal Bit Time
Page 93 and 94: Figure 3.12 Propagation Delay Betwe
Page 95 and 96: 3.6.4 Synchronization t t t t (3.
Page 97 and 98: opposite value is inserted into the
Page 99 and 100: many systems, the bus length will b
Page 101: CHAPTER 4 THE CHALLENGES OF INTERFA
Page 105 and 106: Wearable sensor technology is a new
Page 107 and 108: In traditional bus architectures, o
Page 109 and 110: Figure 4.3 Centralized arbiter with
Page 111 and 112: For the initial prototype design pr
Page 113 and 114: the ID of 31 transmits a ‘0’ (d
Page 115 and 116: Recently, a technique has been prop
Page 117 and 118: procedure, then the address claim p
Page 119 and 120: paradigms are prevalent in the desi
Page 121 and 122: systems possess a higher flexibilit
Page 123 and 124: fixed identifier and hence a fixed
Page 125 and 126: 348sm Cm 47 8 smbit 11-bit hea
Page 127 and 128: est-case latency occurs when the bu
Page 129 and 130: to break the 1 - Wire® network int
Page 131 and 132: ow, is most critical for power deli
Page 133 and 134: computations have device-specific p
Page 135 and 136: Table 4.7 Example results with N 2
Page 137 and 138: 4.3.5 Communication Speed Different
Page 139 and 140: anging” a port pin on a microproc
Page 141 and 142: From Figure 5.1, the block I/O pins
Page 143 and 144: 5.2.2 Command Register In addition
Page 145 and 146: specifies the selected bit value to
Page 147 and 148: with i > m. This process is repeate
Page 149 and 150: Figure 5.6 Interrupt Register. OW_
Page 151 and 152: the INTR pin will be pulled high si
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master reset occurs. Table 5.2 show
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EN_FOW: Enable Force One Wire. Sett
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READ_ROM - Used to read the 64-bit
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5.2.8.1 Single Search ROM (single_s
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5.2.8.3 Scratchpad Memory (scratchp
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5.2.8.4 Command Recognition (cmd_re
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TBF - The Transmit Buffer provides
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compensate for the propagation dela
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Figure 5.15 CAN Module memory map [
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‘0’, fast speed mode will be us
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COMP-SEL: Comparator Select. When t
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Figure 5.18 CAN Status Register. B
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that buffer is given to the CPU and
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Acceptance Mask Registers (accepted
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SJW1, SJW0: Synchronization Jump Wi
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TSEG22 - TSEG10: Time Segment Bits.
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The transmit clock (ttxclk) is used
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5.3.13 CAN Module Transmit Buffer I
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Figure 5.28 CAN Transmit Data Segme
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5.3.20 CAN Node Overview As stated
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Read Digital InputsRead the value o
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the clock high time is either 5 µs
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Yes Perform A/D Conversion on AN0 W
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and GP2 and GP5 as outputs. With th
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external INT pin, and then branches
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Read MCP2515 Rx Buffer for Digital
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When a valid message is received, t
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Table 5.19 Resource Utilization. Re
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For this test, only one CAN node wa
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an Error Frame to be generated. Aft
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messages, acknowledge messages, or
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5.3.21.4 Send Basic Frame Test (sen
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going from one node to 30 nodes (se
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Table 6.1 Resource Utilization. Rev
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6.2.1 Test Verification and Overvie
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has read access to this register. T
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system configuration used for this
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or not depends on the number of rec
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6.4. There are two receiving CAN no
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CHAPTER 7 CONCLUSIONS AND FUTURE WO
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a communication bus reset will occu
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For the synthesizable CAN Controlle
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additional CAN nodes were added to
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Fall-Through Stack A LOW level on t
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In conclusion, the prototype system
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REFERENCES [1] IBM ASIC Products Ap
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[22] “CAN - a brief tutorial for
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[44] Microchip MCP2515 - Stand-Alon
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[67] K. Tindell and A. Burns, “Gu
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[88] “Verilog - A Language Refere
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