DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ... DESIGN OF A CUSTOM ASIC INCORPORATING CAN™ AND 1 ...
TCL Transceive Logic TCP/IP Transmission Control Protocol/Internet Protocol TEC Transmit Error Counter TEDS Transducer Electronic Data Sheet TEMT Transmit Shift Register Empty TO – 92 Transistor Outline Package, Case Style 92 t Q Time Quantum TSOC Thin Small Outline C-lead TTA Time-Triggered Architectures TTCAN Time-Triggered CAN TTL Transistor-Transistor Logic TTP Time-Triggered Protocols TXD Transmit Exchange Data UCSP Ultra Chip Scale Package VCC Common-collector voltage supply VDD Supply voltage VPROH High-level of the Power-on Reset comparator VPUP 1 – Wire® Pull-up Voltage VHDL VHSIC Hardware Description Language VHSIC Very-High-Speed Integrated Circuit w m Worst-case queuing delay of a CAN message ix
ACKNOWLEDGEMENTS I would like to express my sincere gratitude and thanks to Dr. Kenneth G. Ricks for all of his guidance, support, and supervision of this research project. His countless reviews and seemingly endless revisions were instrumental in finalizing this work. I would also like to express my appreciation to all members of my committee: Dr. Jeff Jackson, Dr. Joseph Neggers, Dr. Kenneth G. Ricks, Dr. William Stapleton, and Dr. Larry Wurtz. Thanks to all for their continued belief and support to help make this work possible. x
- Page 1 and 2: DESIGN OF A CUSTOM ASIC INCORPORATI
- Page 3 and 4: ABSTRACT The vast majority of today
- Page 5 and 6: LIST OF ABBREVIATIONS AND SYMBOLS A
- Page 7 and 8: ISO International Organization for
- Page 9: SI Serial In SO Serial Out SOF Star
- Page 13 and 14: 2.4 Types of Devices...............
- Page 15 and 16: 4.3.5 Communication Speed Different
- Page 17 and 18: 5.3.21.1 Synchronization Test (test
- Page 19 and 20: 5.3 Resource Utilization...........
- Page 21 and 22: LIST OF FIGURES 2.1 1 - Wire® Netw
- Page 23 and 24: 4.12 Read-Data Time Slot...........
- Page 25 and 26: 6.4 DS1996 Address Registers ......
- Page 27 and 28: manufacturing process. Structured o
- Page 29 and 30: describes the 1 - Wire® and CAN co
- Page 31 and 32: 2.2 1 - Wire® Overview The basis o
- Page 33 and 34: All 1 - Wire® masters described in
- Page 35 and 36: attachments, microcontroller with b
- Page 37 and 38: Figure 2.3 Bidirectional port pin w
- Page 39 and 40: 2.3.3 Synthesizable 1 - Wire® Bus
- Page 41 and 42: Figure 2.7 UART/RS232 Serial Port I
- Page 43 and 44: hardware. Through control registers
- Page 45 and 46: Table 2.2 1 - Wire® Bus Operations
- Page 47 and 48: 2.3.6 1 - Wire® Search Algorithm F
- Page 49 and 50: detected. This ‘read two bits’
- Page 51 and 52: in Figure 2.15. Alternatively, the
- Page 53 and 54: of the bit, then write the desired
- Page 55 and 56: 2.4.2 Device Functions and Typical
- Page 57 and 58: and development (R&D) investments b
- Page 59 and 60: 2.5 Network Types and Precedents As
TCL Transceive Logic<br />
TCP/IP Transmission Control Protocol/Internet Protocol<br />
TEC Transmit Error Counter<br />
TEDS Transducer Electronic Data Sheet<br />
TEMT Transmit Shift Register Empty<br />
TO – 92 Transistor Outline Package, Case Style 92<br />
t Q<br />
Time Quantum<br />
TSOC Thin Small Outline C-lead<br />
TTA Time-Triggered Architectures<br />
TTCAN Time-Triggered CAN<br />
TTL Transistor-Transistor Logic<br />
TTP Time-Triggered Protocols<br />
TXD Transmit Exchange Data<br />
UCSP Ultra Chip Scale Package<br />
VCC Common-collector voltage supply<br />
VDD Supply voltage<br />
VPROH High-level of the Power-on Reset comparator<br />
VPUP 1 – Wire® Pull-up Voltage<br />
VHDL VHSIC Hardware Description Language<br />
VHSIC Very-High-Speed Integrated Circuit<br />
w m<br />
Worst-case queuing delay of a CAN message<br />
ix
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