UMC UM 613264F-7 2M-Bit SRAM - Smithsonian - The Chip ...
UMC UM 613264F-7 2M-Bit SRAM - Smithsonian - The Chip ... UMC UM 613264F-7 2M-Bit SRAM - Smithsonian - The Chip ...
Report Number: SCA 9609-511 Construction Analysis UMC UM 613264F-7 2M-Bit SRAM Serving the Global Semiconductor Industry Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax: 602-948-1925 e-mail: ice@primenet.com Internet: http://www.ice-corp.com/ice ®
- Page 2 and 3: TITLE INDEX TO TEXT PAGE INTRODUCTI
- Page 4 and 5: Assembly: TECHNOLOGY DESCRIPTION
- Page 6 and 7: Assembly : Questionable Items: 1 No
- Page 8 and 9: ANALYSIS RESULTS II (continued) •
- Page 10 and 11: PROCEDURE The devices were subjecte
- Page 12 and 13: Wire material: 1.1 mil gold wire Di
- Page 14 and 15: Layers: VERTICAL DIMENSIONS Passiva
- Page 16 and 17: UMC UM613264F-7 top bottom Figure 1
- Page 18 and 19: LEADFRAME PLASTIC PACKAGE HEADER DI
- Page 20 and 21: UMC UM613264F-7 DIE DIE Ag PLATING
- Page 22 and 23: UMC UM613264F-7 DAMAGED DURING DECA
- Page 24 and 25: UMC UM613264F-7 PASSIVATION 2 PASSI
- Page 26 and 27: UMC UM613264F-7 METAL 2 ALUMINUM 2
- Page 28 and 29: UMC UM613264F-7 Mag. 8400x ALUMINUM
- Page 30 and 31: UMC UM613264F-7 Ti ADHESION LAYER A
- Page 32 and 33: UMC UM613264F-7 METAL 1 TiN BARRIER
- Page 34 and 35: UMC UM613264F-7 LOCAL OXIDE PRE-MET
- Page 36 and 37: UMC UM613264F-7 LOCAL OXIDE POLY 1
- Page 38 and 39: UMC UM613264F-7 SILICIDE POLY 1 Int
- Page 40 and 41: UMC UM613264F-7 POLY 1 intact delay
- Page 42 and 43: UMC UM613264F-7 WORD Integrated Cir
- Page 44 and 45: UMC UM613264F-7 BIT BIT BIT WORD BI
- Page 46 and 47: UMC UM613264F-7 WORD BIT 1 1 2 WORD
- Page 48 and 49: UMC UM613264F-7 BIT LINE N + S/D PO
- Page 50: UMC UM613264F-7 Figure 36. Optical
Report Number: SCA 9609-511<br />
Construction Analysis<br />
<strong><strong>UM</strong>C</strong> <strong>UM</strong> <strong>613264F</strong>-7<br />
<strong>2M</strong>-<strong>Bit</strong> <strong>SRAM</strong><br />
Serving the Global Semiconductor Industry Since 1964<br />
15022 N. 75th Street<br />
Scottsdale, AZ 85260-2476<br />
Phone: 602-998-9780<br />
Fax: 602-948-1925<br />
e-mail: ice@primenet.com<br />
Internet: http://www.ice-corp.com/ice<br />
®
TITLE<br />
INDEX TO TEXT<br />
PAGE<br />
INTRODUCTION 1<br />
MAJOR FINDINGS 1<br />
TECHNOLOGY DESCRIPTION 2 - 3<br />
ANALYSIS RESULTS I<br />
Assembly 4<br />
ANALYSIS RESULTS II<br />
TABLES<br />
Die Process 5 - 7<br />
Procedure 8<br />
Overall Quality Evaluation 9<br />
Package Markings 10<br />
Wirebond Strength 10<br />
Package Material Analysis 10<br />
Die Material Analysis 10<br />
Horizontal Dimensions 11<br />
Vertical Dimensions 12<br />
- i -
INTRODUCTION<br />
This report describes a construction analysis of the <strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7 2-megabit<br />
<strong>SRAM</strong>. Two devices packaged in a 100-pin Quad Flat Packs (QFPs) were received for<br />
the analysis. One device was mounted for package section and the other was used for<br />
cross section and delayering. <strong>The</strong> devices were date coded 9631.<br />
Questionable Items: 1 None.<br />
Special Features:<br />
MAJOR FINDINGS<br />
• Sub-micron gate lengths (0.3 micron N-channel, 0.4 micron P-channel).<br />
1 <strong>The</strong>se items present possible quality or reliability concerns. <strong>The</strong>y should be discussed<br />
with the manufacturer to determine their possible impact on the intended application<br />
- 1 -
Assembly:<br />
TECHNOLOGY DESCRIPTION<br />
• <strong>The</strong> device was packaged in a 100-pin Quad Flat Pack (QFP).<br />
• External pins (gull-wing) were externally plated with tin-lead (SnPb) solder.<br />
• <strong>The</strong> die was mounted to the header using silver-epoxy.<br />
• Lead-locking provisions (anchors) were present at some pins.<br />
• Die separation by sawn dicing (full depth).<br />
• Wirebonding by the thermosonic ball bond method using 1.1 mil gold wire.<br />
• Numerous pins were not connected.<br />
• Multiple bonding wires were noted.<br />
Die Process:<br />
• Fabrication process: Selective oxidation CMOS process employing P-wells in an N<br />
substrate (no epi).<br />
• Final passivation: Passivation consisted of a layer of nitride over a layer of silicon-<br />
dioxide.<br />
• Metallization: Two levels of metal defined by dry-etch techniques. Metal 2 consisted<br />
of aluminum with a titanium-nitride cap and titanium barrier. Aluminum filled vias<br />
were used at this level. Metal 1 consisted of aluminum with titanium-nitride cap and<br />
barrier. A thin titanium adhesion layer was used under the metal 1 barrier. Metal 1<br />
used tungsten plugs for contacts.<br />
• Design features: No slotted bus lines were present and no bus lines had beveled<br />
corners.<br />
- 2 -
TECHNOLOGY DESCRIPTION (continued)<br />
• Interlevel dielectric: Interlevel dielectric consisted of two layers of glass with a<br />
planarizing glass (SOG) layer in between. <strong>The</strong> filler glass was subjected to an<br />
etchback.<br />
• Pre-metal dielectric: Consisted of reflow glass over various densified oxides. This<br />
layer was reflowed prior to contact cuts only.<br />
• Poly: Two layers of poly were employed. Poly 1 (poly 1 and tungsten silicide) was<br />
used to form all gates, fuses, word lines and to distribute GND in the cell array.<br />
Poly 2 was used in the cell array to form the pull up resistors, bit line contact pads<br />
and to distribute Vcc.<br />
• Diffusions: Standard implanted N+ and P+ diffusions formed the sources/drains of<br />
transistors. Oxide sidewall spacers were used to provide the LDD spacing and were<br />
left in place.<br />
• Wells: P-well in an N substrate.<br />
• Fuses: Poly 1 redundancy fuses were present on the device. No blown fuses were<br />
noted. Passivation and oxide cutouts were made over the fuses. Fuses were located<br />
along the column and row decode and in the periphery.<br />
• Memory array: <strong>The</strong> memory cells consisted of a standard 4T NMOS <strong>SRAM</strong> cell<br />
design. Poly 1 formed the word lines, select gates, storage gates and distributed<br />
GND. Poly 2 formed the “pull up” resistors, bit line contact pads and distributed<br />
Vcc. Metal 1 formed the bit lines and Metal 2 was used to distribute GND.<br />
- 3 -
Assembly :<br />
Questionable Items: 1 None.<br />
Special Features: None.<br />
General Items:<br />
ANALYSIS RESULTS I<br />
• <strong>The</strong> device was packaged in a 100-pin QFP with gull-wing leads.<br />
- 4 -<br />
Figures 1 - 6<br />
• Overall quality: Normal. No cracks or voids were noted on the external or internal<br />
portions of the package.<br />
• Leadframe: <strong>The</strong> leadframe was constructed of copper and plated externally with tin-<br />
lead solder. Plating was complete and no voids were noted. No gaps were present<br />
at the lead exit.<br />
• Dicing: Dicing was by the sawn method (full depth) and was of normal quality with no<br />
large chips or cracks.<br />
• Die attach: Silver-epoxy of normal quality. No significant voiding was noted.<br />
• Wirebonding: <strong>The</strong>rmosonic ball bond method using 1.1 mil gold wire. Bonds were<br />
well formed and were of good placement. Bond pull strengths were good with no<br />
bond lifts (see page 10).<br />
1 <strong>The</strong>se items present possible quality or reliability concerns. <strong>The</strong>y should be discussed<br />
with the manufacturer to determine their possible impact on the intended application.
Die Process :<br />
Questionable Items: 1 None.<br />
Special Features:<br />
ANALYSIS RESULTS II<br />
- 5 -<br />
Figures 7 - 36<br />
• Sub-micron gate lengths (0.3 micron N-channel, 0.4 micron P-channel).<br />
General Items:<br />
• Fabrication process: Selective oxidation CMOS process employing P-wells in an N<br />
substrate (no epi). No significant problems were found in the process.<br />
• Design implementation: Die layout was clean. Alignment was good at all levels.<br />
No slotted bus lines were present and no bus lines had beveled corners.<br />
• Surface defects: No toolmarks, masking defects, or contamination areas were found.<br />
• Final passivation: Passivation consisted of a layer of nitride over a layer of silicon-<br />
dioxide. Passivation integrity tests indicated defect-free passivation. Edge seal was<br />
good.<br />
• Metallization: Two levels of metallization. Metal 2 consisted of aluminum with a<br />
titanium-nitride cap and titanium barrier. Metal 2 vias were aluminum filled. Metal 1<br />
consisted of aluminum with a titanium-nitride cap and barrier and tungsten filled plugs<br />
and a titanium-nitride cap and barrier. A thin titanium adhesion layer was present under<br />
the Metal 1 barrier.<br />
1 <strong>The</strong>se items present possible quality or reliability concerns. <strong>The</strong>y should be discussed<br />
with the manufacturer to determine their possible impact on the intended application.
ANALYSIS RESULTS II (continued)<br />
• Metal patterning: Both metal layers were defined by a dry etch of good quality. No<br />
problems were found.<br />
• Metal defects: No notching or voiding of either metal layer was found. No silicon<br />
nodules were found following the removal of the metal layers.<br />
• Metal step coverage: Virtually no metal thinning was noted at either metal layer due<br />
to Metal 2 filled vias and Metal 1 tungsten plugs.<br />
• Interlevel dielectric: Interlevel dielectric consisted of two layers of glass with a<br />
planarizing glass (SOG) layer in between. <strong>The</strong> filler glass was subjected to an<br />
etchback. No problems were found with the dielectric layers.<br />
• Pre-metal dielectric: Reflow glass over various densified oxides were used under<br />
Metal 1. Reflow was performed prior to contact cuts. No problems were found with<br />
any of these layers.<br />
• Poly: Two layers of poly. Poly 1 (poly 1 and tungsten silicide) was used to form all<br />
gates and fuses on the die and the word and GND lines in the array. Poly 2 was<br />
used in the cell array to form bit line contact pads, “pull up” resistors and to<br />
distribute Vcc.<br />
• Isolation: Local oxide (LOCOS). No problems were present at the birdsbeaks or<br />
elsewhere. No step was noted in the local oxide.<br />
• Diffusions: Standard implanted N+ and P+ diffusions were used for sources and<br />
drains. An LDD process was used employing oxide sidewall spacers. <strong>The</strong> spacers<br />
were left in place. No problems were found in any of these areas.<br />
• Wells: P-wells were used in an N substrate (no epi present). No problems were<br />
apparent.<br />
• Buried contacts: Interpoly/buried contacts were used in the cell array. No problems<br />
were found.<br />
- 6 -
ANALYSIS RESULTS II (continued)<br />
• Fuses: All polycide 1 redundancy fuses had passivation and oxide cutouts over<br />
them. No blown fuses were present. Fuses were located along the column and row<br />
decodes and in the periphery.<br />
• Memory array: <strong>The</strong> memory cells consisted of a standard 4T NMOS <strong>SRAM</strong> cell<br />
design. Poly 1 formed the word lines, select gates, storage gates and distributed<br />
GND. Poly 2 formed the “pull up” resistors, bit line contact pads, and distributed<br />
Vcc. Metal 1 formed the bit lines and Metal 2 was used to distribute GND. Cell<br />
pitch was 2.5 x 4.5 microns.<br />
- 7 -
PROCEDURE<br />
<strong>The</strong> devices were subjected to the following analysis procedures:<br />
External inspection<br />
X-ray<br />
Package section<br />
Decapsulate<br />
Internal optical inspection<br />
SEM inspection of assembly features and passivation<br />
Wirepull test<br />
Passivation integrity test<br />
Delayer to Metal 2 and inspect<br />
Aluminum removal (Metal 2) and inspect barrier<br />
Delayer to Metal 1 and inspect<br />
Aluminum removal (Metal 1) and inspect barrier<br />
Delayer to poly/substrate and inspect<br />
Die sectioning (90° for SEM) *<br />
Measure horizontal dimensions<br />
Measure vertical dimensions<br />
Die material analysis<br />
* Delineation of cross-sections is by silicon etch unless otherwise indicated.<br />
- 8 -
OVERALL QUALITY EVALUATION: Overall Rating: Normal<br />
DETAIL OF EVALUATION<br />
Package integrity N<br />
Die placement G<br />
Wirebond placement G<br />
Wire spacing G<br />
Wirebond quality G<br />
Die attach quality N<br />
Dicing quality N<br />
Die attach method Silver-epoxy<br />
Dicing method Sawn (full depth)<br />
Wirebond method <strong>The</strong>rmosonic ball bonds using 1.1 mil gold wire.<br />
Die surface integrity:<br />
Toolmarks (absence) G<br />
Particles (absence) G<br />
Contamination (absence) G<br />
Process defects (absence) G<br />
General workmanship G<br />
Passivation integrity G<br />
Metal definition G<br />
Metal integrity G<br />
Metal registration N<br />
Contact coverage N<br />
Contact registration G<br />
G = Good, P = Poor, N = Normal, NP = Normal/Poor<br />
- 9 -
Wire material: 1.1 mil gold wire<br />
Die pad material: aluminum<br />
Package lands: silver<br />
Sample # 1<br />
# of wires pulled: 45<br />
Bond lifts: 0<br />
Force to break - high: 15.0g<br />
- low: 7.5g<br />
- avg.: 12.5g<br />
- std. dev.: 1.6<br />
PACKAGE MARKINGS<br />
(Logo) <strong><strong>UM</strong>C</strong><br />
<strong>UM</strong>61L3264 F-7<br />
9631S RM 6G53<br />
WIREBOND STRENGTH<br />
PACKAGE MATERIAL ANALYSIS<br />
Leadframe: Copper (Cu)<br />
Internal plating: Silver (Ag)<br />
External plating: Tin-lead solder (SnPb)<br />
Die attach: Silver (Ag) epoxy<br />
DIE MATERIAL ANALYSIS<br />
Passivation: Layer of nitride over a layer of silicon-dioxide.<br />
Metal 2: Aluminum with a titanium-nitride cap and titanium barrier.<br />
Interlevel dielectric: Two layers of silicon-dioxide with a spin-on-glass (SOG).<br />
Metal 1: Aluminum with titanium-nitride cap and barrier and<br />
titanium adhesion layer.<br />
Pre-metal dielectric: Reflow glass (probably BPSG) over various densified oxides.<br />
Poly 2: Poly.<br />
Poly 1: Poly with tungsten silicide.<br />
- 10 -
HORIZONTAL DIMENSIONS<br />
Die size: 6.1 x 6.7 mm (240 x 265 mils)<br />
Die area: 41 mm 2 (63,600 mils 2 )<br />
Min pad size: 0.1 x 0.1 mm (4.2 x 4.2 mils)<br />
Min pad window: 0.09 x 0.09 mm (3.9 x 3.9 mils)<br />
Min pad space: 20 microns<br />
Min metal 2 width: 0.6 micron<br />
Min metal 2 space: 0.6 micron<br />
Min metal 2 pitch: 1.2 micron<br />
Min metal 1 width: 0.6 micron<br />
Min metal 1 space: 0.6 micron<br />
Min metal 1 pitch: 1.2 micron<br />
Min via M2 - M1: 0.5 micron<br />
Min contact: 0.5 micron<br />
Min poly 1 width: 0.3 micron<br />
Min poly 1 space: 0.5 micron<br />
Min gate length * - (N-channel): 0.3 micron<br />
- (P-channel): 0.4 micron<br />
Cell size: 11.25 microns 2<br />
Cell pitch: 2.5 x 4.5 microns<br />
* Physical gate length.<br />
- 11 -
Layers:<br />
VERTICAL DIMENSIONS<br />
Passivation 2: 0.65 micron<br />
Passivation 1: 0.4 micron<br />
Metal 2 - cap: 0.05 micron (approx.)<br />
- aluminum: 0.9 micron<br />
- barrier: 0.08 micron (approx.)<br />
Interlevel dielectric - glass 2: 0.4 micron<br />
- glass 1: 0.8 micron (average)<br />
Metal 1 - cap: 0.06 micron (approx.)<br />
- aluminum: 0.5 micron<br />
- barrier: 0.1 micron<br />
- adhesion layer: 0.1 micron<br />
Pre-metal dielectric: 0.65 micron (average)<br />
Poly 2: 0.05 micron (approx.)<br />
Interpoly oxide: 0.2 micron<br />
Poly 1 - silicide: 0.12 micron<br />
- poly 1: 0.17 micron<br />
Local oxide: 0.3 micron<br />
N+ S/D diffusion: 0.14 micron<br />
P+ S/D diffusion: 0.25 micron<br />
P- well: 3.5 microns<br />
- 12 -
INDEX TO FIGURES<br />
ASSEMBLY Figures 1 - 6<br />
DIE LAYOUT AND IDENTIFICATION Figures 7 - 8<br />
PHYSICAL DIE STRUCTURES Figures 9 - 36<br />
COLOR DRAWING OF DIE STRUCTURE Figure 25<br />
FUSES Figures 26 and 27<br />
MEMORY CELLS Figures 28 - 34<br />
GENERAL CIRCUIT LAYOUT Figure 35<br />
INPUT/OUTPUT LAYOUT Figure 36<br />
- ii -
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
top<br />
bottom<br />
Figure 1. Package photographs of the <strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7. Mag. 4x.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
PIN 1<br />
top<br />
side<br />
Figure 2. X-ray views of the package. Mag. 3.8x.<br />
Integrated Circuit Engineering Corporation
LEADFRAME<br />
PLASTIC PACKAGE<br />
HEADER<br />
DIE<br />
Figure 3. Package section view of general construction Mag. 13x.<br />
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
PLASTIC PACKAGE<br />
PLASTIC PACKAGE<br />
Cu LEADFRAME<br />
Mag. 40x<br />
Cu LEADFRAME<br />
Mag. 340x<br />
Figure 4. Package section views illustrating lead forming and lead exit.<br />
Integrated Circuit Engineering Corporation<br />
SnPb TINNING
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
DIE<br />
DIE<br />
Ag PLATING<br />
Ag EPOXY DIE ATTACH<br />
Mag. 100x<br />
Mag. 500x<br />
Cu HEADER<br />
Ag EPOXY<br />
Figure 5. Package section views illustrating dicing and die attach.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
Au<br />
Mag. 625x<br />
Au<br />
BOND PAD<br />
Mag. 660x<br />
Figure 6. SEM views of typical wirebonding. 60°.<br />
Integrated Circuit Engineering Corporation<br />
LEADFRAME
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
DAMAGED DURING<br />
DECAPSULATION<br />
Figure 7. Whole die photograph of the <strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7. Mag. 13x.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
Mag. 200x<br />
Mag. 500x<br />
Figure 8. Optical views of markings on the die surface.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
PASSIVATION 2<br />
PASSIVATION 1<br />
METAL 2<br />
POLY 1<br />
POLY 1<br />
N + S/D<br />
PLUG<br />
METAL 1<br />
PLUG<br />
Figure 9. SEM section views illustrating general structure. Mag. 13,000x.<br />
Integrated Circuit Engineering Corporation<br />
METAL 1
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
Mag. 5700x<br />
Mag. 15,000x<br />
Figure 10. Perspective SEM views of overlay passivation coverage. 60°.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
METAL 2<br />
AL<strong>UM</strong>IN<strong>UM</strong> 2<br />
PASSIVATION 2<br />
Mag. 26,000x<br />
TiN CAP<br />
Ti BARRIER<br />
DEBRIS<br />
Mag. 52,000x<br />
Figure 11. SEM section views of metal 2 line profiles.<br />
Integrated Circuit Engineering Corporation<br />
PASSIVATION 1<br />
PASSIVATION 1
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
METAL 2<br />
METAL 2<br />
Mag. 6000x<br />
Mag. 10,000x<br />
Figure 12. Topological SEM views of metal 2 patterning. 0°.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
Mag. 8400x<br />
AL<strong>UM</strong>IN<strong>UM</strong> 2<br />
Mag. 26,000x<br />
TiN CAP<br />
Figure 13. Perspective SEM views of metal 2 coverage. 60°.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
Mag. 52,000x, 45°<br />
PASSIVATION 1<br />
METAL 1<br />
Ti BARRIER<br />
Mag. 26,000x<br />
METAL 2<br />
Figure 14. SEM views of barrier coverage and metal 2-to-metal 1 via.<br />
Integrated Circuit Engineering Corporation<br />
INTERLEVEL<br />
DIELECTRIC
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
Ti ADHESION<br />
LAYER<br />
AL<strong>UM</strong>IN<strong>UM</strong> 1<br />
TiN BARRIER<br />
INTERLEVEL DIELECTRIC<br />
METAL 1<br />
PRE-METAL DIELECTRIC<br />
TiN CAP<br />
Mag. 26,000x<br />
PRE-METAL DIELECTRIC<br />
Mag. 52,000x<br />
Figure 15. SEM section view of metal 1 line profiles.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
METAL 1<br />
METAL 1<br />
Mag. 4000x<br />
Mag. 7400x<br />
Figure 16. Topological SEM views of metal 1 patterning. 0°.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
METAL 1<br />
TiN BARRIER<br />
Mag. 6500x<br />
TiN CAP<br />
AL<strong>UM</strong>IN<strong>UM</strong> 1<br />
W PLUG<br />
Mag. 26,000x<br />
Figure 17. Perspective SEM views of metal 1 step coverage. 60°.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
W PLUG<br />
Mag. 52,000x<br />
AL<strong>UM</strong>IN<strong>UM</strong> 1<br />
W PLUG<br />
glass etch, Mag. 35,000x<br />
TiN BARRIER<br />
TiN CAP<br />
Figure 18. SEM views of barrier coverage and metal 1 contact.<br />
Integrated Circuit Engineering Corporation<br />
TiN BARRIER<br />
PRE-METAL DIELECTRIC<br />
POLY 1
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
LOCAL OXIDE<br />
PRE-METAL<br />
DIELECTRIC<br />
POLY 1<br />
P +S/D<br />
INTERLEVEL DIELECTRIC<br />
METAL 1<br />
W PLUG<br />
INTERLEVEL DIELECTRIC<br />
METAL 1<br />
W PLUG<br />
INTERLEVEL DIELECTRIC<br />
METAL 1<br />
W PLUG<br />
POLY 1<br />
N +S/D<br />
POLY 1<br />
Integrated Circuit Engineering Corporation<br />
PRE-METAL<br />
DIELECTRIC<br />
Figure 19. SEM section views of metal 1 contacts. Silicon etch, Mag. 26,000x.
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
DIFFUSION<br />
POLY 1<br />
DIFFUSION<br />
Mag. 5500x<br />
Mag. 11,000x<br />
POLY 1<br />
Figure 20. Topological SEM views of poly patterning. 0°.<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
LOCAL OXIDE<br />
POLY 1<br />
DIFFUSION<br />
POLY 1<br />
DIFFUSION<br />
POLY 1<br />
DIFFUSION<br />
Figure 21. Perspective SEM views of poly 1 coverage. 60°.<br />
Integrated Circuit Engineering Corporation<br />
Mag. 6500x<br />
Mag. 26,000x<br />
Mag. 26,000x
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
SIDEWALL SPACER<br />
PRE-METAL DIELECTRIC<br />
SILICIDE<br />
POLY 1<br />
PRE-METAL DIELECTRIC<br />
SILICIDE<br />
POLY 1<br />
N + S/D<br />
PRE-METAL DIELECTRIC<br />
SILICIDE<br />
POLY 1<br />
P + S/D<br />
Figure 22. SEM section views of typical transistors. Mag. 52,000x.<br />
Integrated Circuit Engineering Corporation<br />
W PLUG<br />
W PLUG<br />
W PLUG<br />
glass etch<br />
N-channel<br />
P-channel
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
SILICIDE<br />
POLY 1<br />
Integrated Circuit Engineering Corporation<br />
Figure 23. SEM section view of a typical local oxide birdsbeak. Mag. 52,000x.<br />
P- WELL<br />
N- SUBSTRATE<br />
LOCAL OXIDE<br />
Figure 24. Optical section view of the well structure. Mag. 800x.
CAP 1<br />
BARRIER 1<br />
METAL 2<br />
INTERLEVEL DIELECTRIC<br />
PASSIVATION 2<br />
PASSIVATION 1<br />
PRE-METAL DIELECTRIC<br />
BARRIER 2<br />
,,,,,,,,,,<br />
W SILICIDE<br />
POLY 1<br />
,,,,,,,,,,<br />
P+ S/D<br />
N+ S/D<br />
P-WELL<br />
,,,,,,,,,,<br />
N-SUBSTRATE<br />
Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly,<br />
Red = Diffusion, and Gray = Substrate<br />
METAL 1<br />
Figure 25. Color cross section drawing illustrating device structure.<br />
W PLUG<br />
CAP 2<br />
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
Integrated Circuit Engineering Corporation
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
POLY 1<br />
intact<br />
delayered<br />
Figure 26. Topological SEM views of fuses. Mag. 4400x, 0°.<br />
Integrated Circuit Engineering Corporation<br />
PASSIVATION<br />
CUTOUT
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
intact<br />
POLY 1<br />
delayered<br />
Figure 27. Perspective SEM views of fuses. Mag. 5000x, 45°.<br />
Integrated Circuit Engineering Corporation<br />
CUTOUT<br />
PASSIVATION
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
WORD<br />
Integrated Circuit Engineering Corporation<br />
metal 2<br />
metal 1<br />
unlayered<br />
Figure 28. Perspective SEM views of a <strong>SRAM</strong> cell array. Mag. 13,000x, 60°.<br />
GND<br />
GND<br />
V CC<br />
BIT<br />
BIT
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
POLY 1<br />
Mag. 26,000x<br />
Mag. 52,000x<br />
POLY 2<br />
Figure 29. Detailed SEM views of the <strong>SRAM</strong> cell array. 60°.<br />
Integrated Circuit Engineering Corporation<br />
V CC
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
BIT<br />
BIT<br />
BIT<br />
WORD<br />
BIT<br />
GND<br />
GND<br />
GND<br />
V CC<br />
Integrated Circuit Engineering Corporation<br />
metal 2<br />
metal 1<br />
unlayered<br />
Figure 30. Topological SEM views of the <strong>SRAM</strong> cell array. Mag. 6500x.
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
metal 2<br />
metal 1<br />
Figure 31. Topological SEM views of the <strong>SRAM</strong> cell array. Mag. 13,000x.<br />
Integrated Circuit Engineering Corporation<br />
GND<br />
BIT<br />
BIT
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
WORD<br />
BIT<br />
1<br />
1<br />
2<br />
WORD<br />
unlayered<br />
R1<br />
3 4<br />
Figure 32. Topological SEM views and schematic of the <strong>SRAM</strong> cell array. Mag. 13,000x.<br />
R1<br />
R2<br />
R2<br />
3<br />
4<br />
2<br />
Integrated Circuit Engineering Corporation<br />
V CC<br />
GND<br />
BIT
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
POLY 1<br />
SELECT<br />
GATE<br />
BIT LINE CONTACT<br />
Mag. 13,000x<br />
METAL 1 BIT LINE CONTACT<br />
N + S/D N + S/D<br />
Mag. 26,000x<br />
POLY 2 “PULL UP”<br />
RESISTOR<br />
POLY 2<br />
CONTACT<br />
PAD<br />
Figure 33. SEM section views of <strong>SRAM</strong> cell array.<br />
Integrated Circuit Engineering Corporation<br />
GND<br />
POLY 2 “PULL UP”<br />
RESISTOR<br />
POLY 1<br />
SELECT<br />
GATE
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
BIT LINE<br />
N + S/D<br />
POLY 1<br />
SELECT<br />
GATE<br />
POLY 2 CONTACT<br />
PAD POLY 2 “PULL UP”<br />
RESISTOR<br />
POLY 1 SELECT<br />
GATE<br />
N + S/D<br />
N + S/D<br />
Figure 34. Detailed SEM views of <strong>SRAM</strong> cell array. Mag. 52,000x.<br />
Integrated Circuit Engineering Corporation<br />
POLY 2 “PULL UP”<br />
RESISTOR
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
Figure 35. Optical views of general circuitry. Mag. 320x.<br />
Integrated Circuit Engineering Corporation<br />
intact<br />
metal 1<br />
unlayered
<strong><strong>UM</strong>C</strong> <strong>UM</strong><strong>613264F</strong>-7<br />
Figure 36. Optical views of I/O structure. Mag. 320x.<br />
Integrated Circuit Engineering Corporation<br />
intact<br />
metal 1<br />
unlayered