Xilinx CPLD Libraries Guide

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CB16CLED About Design Elements Macro: 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear Supported Architectures This design element is supported in the following architectures only: • XC9500XL • CoolRunner XPLA3 • CoolRunner-II Introduction This design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binary counter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High and UP is Low during the Low-to- High clock transition. The Q outputs increment when CE and UP are High. The counter ignores clock transitions when CE is Low. For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TC output is High when all Q outputs and UP are Low. Create larger counters by connecting the CEO output of each stage to the CE input of the next stage and connecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input or use the TC output if it does not. For CPLD parts, see “CB2X1”, “CB4X1”, “CB8X1”, “CB16X1” for high-performance cascadable, bidirectional counters. This counter is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can simulate power-on by applying a High-level pulse on the PRLD global net. Logic Table Inputs Outputs CLR L CE C UP Dz – D0 Qz – Q0 TC CEO 1 X X X X X 0 0 0 0 1 X › X Dn Dn TC CEO CPLD Libraries Guide 88 www.xilinx.com ISE 10.1
About Design Elements Inputs Outputs CLR L CE C UP Dz – D0 Qz – Q0 TC CEO 0 0 0 X X X No change No change 0 0 0 1 › 1 X Inc TC CEO 0 0 1 › 0 X Dec TC CEO z = bit width - 1 TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) CEO = TC•CE Design Entry Method This design element is only for use in schematics. For More Information • See the appropriate CPLD User Guide. • See the appropriate CPLD Data Sheets. CPLD Libraries Guide ISE 10.1 www.xilinx.com 89
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ISE 10.1 CPLD Libraries Guide
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Table of Contents About this Guide.
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About this Guide This guide is part
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Design Element Description BUFE4 Ma
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Design Element Description Function
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About Design Elements For More Info
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About Design Elements B0 for ACC16)
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About Design Elements • For twos-
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About Design Elements B0 for ACC8)
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About Design Elements ADD16 Macro:
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