Xilinx CPLD Libraries Guide

About Design Elements
BUFT8
Macro: 8-Bit Internal 3-State Buffers with Active Low Enable
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
Introduction
This design element is a multiple 3-state buffer with inputs I7 – I0 and outputs O7 – O0 and active-Low output
enable (T). When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T
is High, the output is high impedance (Z state or off). The outputs of the buffers are connected to horizontal
longlines in FPGA architectures.
The output of separate BUFT symbols can be tied together to form a bus or a multiplexer. Make sure that only
one T is Low at one time. For CPLD devices, BUFT output nets assume the High logic level when all connected
BUFE/BUFT buffers are disabled. For FPGAs, when all BUFTs on a net are disabled, the net is High. For correct
simulation of this effect, a PULLUP element must be connected to the net. NGDBuild inserts a PULLUP element
if one is not connected so that back-annotation simulation reflects the true state of the device.
Logic Table
Inputs Outputs
T I O
1 X Z
0 1 1
0 0 0
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 83