Xilinx CPLD Libraries Guide

BUFT
Primitive: Internal 3-State Buffer with Active Low Enable
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
Introduction
About Design Elements
This design element is a single 3-state buffer with input I and an output of O and active-Low output enable (T).
When T is Low, data on the input of the buffer is transferred to the corresponding output. When T is High,
the output is high impedance (Z state or off). The output of the buffer is connected to a horizontal longline
in FPGA architectures.
The output of separate BUFT symbols can be tied together to form a bus or a multiplexer. Make sure that only
one T is Low at one time. For CPLD devices, BUFT output nets assume the High logic level when all connected
BUFE/BUFT buffers are disabled. For FPGAs, when all BUFTs on a net are disabled, the net is High. For correct
simulation of this effect, a PULLUP element must be connected to the net. NGDBuild inserts a PULLUP element
if one is not connected so that back-annotation simulation reflects the true state of the device.
Logic Table
Inputs Outputs
T I O
1 X Z
0 1 1
0 0 0
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
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