Xilinx CPLD Libraries Guide

About Design Elements
BUFGTS
Primitive: Global 3-State Input Buffer
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
This design element distributes global output-enable signals throughout the output pad drivers of CPLD devices.
Global Three-State (GTS) control pins are available on these CPLD devices. Consult device data sheets for
availability.
This element always acts as an input buffer. To use it in a schematic, connect the input of the BUFGTS symbol
to an IPAD or an IOPAD representing the GTS signal source. GTS signals generated on-chip must be passed
through an OBUF-type buffer before they are connected to this element.
For global 3-state control, the output of this element normally connects to the E input of a 3-state output buffer
symbol, OBUFE. The global 3-state control signal may pass through an inverter or control an OBUFT symbol
to perform an active-low output-enable. The same 3-state control signal may even be used both inverted and
non-inverted to enable alternate groups of device outputs. The output of BUFGTS may also be used as an
ordinary input signal to other logic elsewhere in the design. Each BUFGTS can control any number of output
buffers in a design.
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 79