Xilinx CPLD Libraries Guide

About Design Elements
BUFE16
Macro: 16-Bit Internal 3-State Buffer with Active High Enable
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
Introduction
This design element is a multiple 3-state buffer with inputs of I15 – I0 and outputs of O15 – O0 and an active-High
output enable (E). When E is High, data on the inputs of the buffers is transferred to the corresponding outputs.
When E is Low, the output is high impedance (Z state or Off). The outputs of the buffers are connected to
horizontal longlines in FPGA architectures. The outputs of separate BUFE elements can be tied together to
form a bus or a multiplexer. Make sure that only one E is High at any one time. If none of the E inputs is
active-High, a “weak-keeper” circuit keeps the output bus from floating but does not guarantee that the bus
remains at the last value driven onto it.
Logic Table
Inputs Outputs
E I O
0 X Z
1 1 1
1 0 0
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
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