Xilinx CPLD Libraries Guide

BUFE
Primitive: Internal 3-State Buffer with Active High Enable
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
Introduction
About Design Elements
This design element is a single, 3-state buffer with inputs I and output O, and an active-High output enable (E).
When E is High, data on the input of the buffer is transferred to the corresponding output. When E is Low, the
output is high impedance (Z state or Off). The outputs of the buffers are connected to horizontal longlines
in FPGA architectures.
The outputs of separate symbols for this entity can be tied together to form a bus or a multiplexer. Make sure
that only one E is High at any one time. If none of the E inputs is active-High, a “weak-keeper” circuit keeps
the output bus from floating but does not guarantee that the bus remains at the last value driven onto it. For
certain CPLD devices, output from nets assume the High logic level when all connected BUFE/BUFT buffers
are disabled. For FPGA devices, elements need a PULLUP element connected to their output. NGDBuild
inserts a PULLUP element if one is not connected.
Logic Table
Inputs Outputs
E I O
0 X Z
1 1 1
1 0 0
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
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