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Xilinx CPLD Libraries Guide

Xilinx CPLD Libraries Guide

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About Design Elements<br />

BRLSHFT4<br />

Macro: 4-Bit Barrel Shifter<br />

Supported Architectures<br />

This design element is supported in the following architectures only:<br />

• XC9500XL<br />

• CoolRunner XPLA3<br />

• CoolRunner-II<br />

Introduction<br />

This design element is a 4-bit barrel shifter that can rotate four inputs (I3 – I0) up to four places. The control<br />

inputs (S1 and S0) determine the number of positions, from one to four, that the data is rotated. The four outputs<br />

(O3 – O0) reflect the shifted data inputs.<br />

Logic Table<br />

Inputs Outputs<br />

S1 S0 I0 I1 I2 I3 O0 O1 O2 O3<br />

0 0 a b c d a b c d<br />

0 1 a b c d b c d a<br />

1 0 a b c d c d a b<br />

1 1 a b c d d a b c<br />

Design Entry Method<br />

This design element is only for use in schematics.<br />

For More Information<br />

• See the appropriate <strong>CPLD</strong> User <strong>Guide</strong>.<br />

• See the appropriate <strong>CPLD</strong> Data Sheets.<br />

<strong>CPLD</strong> <strong>Libraries</strong> <strong>Guide</strong><br />

ISE 10.1 www.xilinx.com 65

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