Xilinx CPLD Libraries Guide

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SRD16RE About Design Elements Macro: 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset Supported Architectures This design element is supported in the following architectures only: CoolRunner-II Introduction This design element is a dual edge triggered shift register with shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE), and synchronous reset (R) inputs. The R input, when High, overrides all other inputs during the Low-to-High or High-to-Low clock (C) transition and resets the data outputs (Q) Low. When CE is High and R is Low, the data on the SLI is loaded into the first bit of the shift register during the Low-to-High clock or High-to-Low (C) transition and appears on the Q0 output. During subsequent clock transitions, when CE is High and R is Low, data shifts to the next highest bit position as new data is loaded into Q0. The register ignores clock transitions when CE is Low. Registers can be cascaded by connecting the last Q output of one stage to the SLI input of the next stage and connecting clock, CE, and R in parallel. This register is asynchronously cleared, outputs Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Logic Table Inputs Outputs R CE SLI C Q0 Qz – Q1 1 X X › 0 0 1 X X fl 0 0 0 0 X X No Change No Change 0 1 1 › 1 qn-1 0 1 1 fl 1 qn-1 0 1 0 › 0 qn-1 0 1 0 fl 0 qn-1 z = bitwidth -1 qn-1 = state of referenced output one setup time prior to active clock transition CPLD Libraries Guide 582 www.xilinx.com ISE 10.1
About Design Elements Design Entry Method This design element is only for use in schematics. For More Information • See the appropriate CPLD User Guide. • See the appropriate CPLD Data Sheets. CPLD Libraries Guide ISE 10.1 www.xilinx.com 583
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ISE 10.1 CPLD Libraries Guide
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Table of Contents About this Guide.
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About this Guide This guide is part
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Design Element Description BUFE4 Ma
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Design Element Description Function
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About Design Elements This section
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About Design Elements For More Info
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About Design Elements B0 for ACC16)
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About Design Elements • For twos-
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About Design Elements B0 for ACC8)
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About Design Elements ADD16 Macro:
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About Design Elements BRLSHFT4 Macr
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About Design Elements BUFG BUFG_ins
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About Design Elements Design Entry
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About Design Elements Inputs Output
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About Design Elements Logic Table I
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