Xilinx CPLD Libraries Guide

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SR4CLED Macro: 4-Bit Shift Register with Clock Enable and Asynchronous Clear Supported Architectures This design element is supported in the following architectures only: • XC9500XL • CoolRunner XPLA3 • CoolRunner-II Introduction About Design Elements This design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D), parallel outputs (Q), and four control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), and asynchronous clear (CLR). The register ignores clock transitions when (CE) and (L) are Low. The asynchronous clear, when High, overrides all other inputs and resets the data outputs (Qn) Low. When (L) is High and (CLR) is Low, the data on the (D) inputs is loaded into the corresponding (Q) bits of the register. When (CE) is High and (L) and (CLR) are Low, data is shifted right or left, depending on the state of the LEFT input. If LEFT is High, data on the SLI is loaded into (Q0) during the Low-to-High clock transition and shifted left (for example, to Q1 or Q2) during subsequent clock transitions. If LEFT is Low, data on the SRI is loaded into the last (Q) output during the Low-to-High clock transition and shifted right during subsequent clock transitions. The logic tables indicate the state of the (Q) outputs under all input conditions. This register is asynchronously cleared, outputs Low, when power is applied. Logic Table Inputs Outputs CLR L CE LEFT SLI SRI D3 – D0 C Q0 Q3 Q2 – Q1 1 X X X X X X X 0 0 0 0 1 X X X X D3– D0 › D0 D3 Dn 0 0 0 X X X X X No Change No Change 0 0 1 1 SLI X X › SLI q2 qn-1 No Change CPLD Libraries Guide 556 www.xilinx.com ISE 10.1
About Design Elements Inputs Outputs CLR L CE LEFT SLI SRI D3 – D0 C Q0 Q3 Q2 – Q1 0 0 1 0 X SRI X › q1 SRI qn+1 qn-1 and qn+1 = state of referenced output one setup time prior to active clock transition. Design Entry Method This design element is only for use in schematics. For More Information • See the appropriate CPLD User Guide. • See the appropriate CPLD Data Sheets. CPLD Libraries Guide ISE 10.1 www.xilinx.com 557
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ISE 10.1 CPLD Libraries Guide
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Table of Contents About this Guide.
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About this Guide This guide is part
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Design Element Description BUFE4 Ma
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Design Element Description Function
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About Design Elements This section
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About Design Elements For More Info
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About Design Elements B0 for ACC16)
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About Design Elements • For twos-
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About Design Elements B0 for ACC8)
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About Design Elements ADD16 Macro:
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