Xilinx CPLD Libraries Guide

About Design Elements
);
-- End of PULLDOWN_inst instantiation
Verilog Instantiation Template
// PULLDOWN: I/O Buffer Weak Pull-down
// All FPGA
// Xilinx HDL Libraries Guide, version 10.1.1
PULLDOWN PULLDOWN_inst (
.O(O) // Pulldown output (connect directly to top-level port)
);
// End of PULLDOWN_inst instantiation
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 537