Xilinx CPLD Libraries Guide

PULLDOWN
Primitive: Resistor to GND for Input Pads, Open-Drain, and 3-State Outputs
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This resistor element is connected to input, output, or bidirectional pads to guarantee a logic Low level for
nodes that might float.
Port Descriptions
Name Direction Width Function
O Output 1-Bit Pulldown output (connect directly to top level port)
Design Entry Method
Instantiation Yes
Inference Recommended
Coregen and wizards No
Macro support No
This design element can be used in schematics.
This element can be connected to a net in the following locations on a top-level schematic file:
• A net connected to an input IO Marker
• A net connected to both an output IO Marker and 3-statable IO element, such as an OBUFT.
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- PULLDOWN: I/O Buffer Weak Pull-down
-- All FPGA
-- Xilinx HDL Libraries Guide, version 10.1.1
PULLDOWN_inst : PULLDOWN
port map (
O => O -- Pulldown output (connect directly to top-level port)
CPLD Libraries Guide
536 www.xilinx.com ISE 10.1