Xilinx CPLD Libraries Guide

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OBUFT4 Macro: 4-Bit 3-State Output Buffers with Active-Low Output Enable Supported Architectures This design element is supported in the following architectures only: • XC9500XL • CoolRunner XPLA3 • CoolRunner-II Introduction About Design Elements This design element is a multiple, 3-state output buffer with input I, output O, and active-Low output enables (T). This element uses the LVTTL standard and has selectable drive and slew rates using the DRIVE and SLOW or FAST constraints. The defaults are DRIVE=12 mA and SLOW slew. When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, the output is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is needed with a 3-state capability, such as the case when building bidirectional I/O. Logic Table Inputs Outputs T I O 1 X Z 0 I F Design Entry Method This design element is only for use in schematics. Available Attributes Attribute Type Allowed Values Default Description DRIVE Integer 2, 4, 6, 8, 12, 16, 24 12 Specifies the output current drive strength of the I/O. It is suggested that you set this to the lowest setting tolerable for the design drive and timing requirements. CPLD Libraries Guide 510 www.xilinx.com ISE 10.1
About Design Elements Attribute Type Allowed Values Default Description IOSTANDARD String Consult the product Data Sheet. "DEFAULT" Specifies the I/O standard to be used for this output. SLEW String "SLOW" or "FAST” "SLOW” Specifies the slew rate of the output driver. Consult the product Data Sheet for recommendations of the best setting for this attribute. For More Information • See the appropriate CPLD User Guide. • See the appropriate CPLD Data Sheets. CPLD Libraries Guide ISE 10.1 www.xilinx.com 511
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ISE 10.1 CPLD Libraries Guide
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Table of Contents About this Guide.
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Design Element Description Function
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About Design Elements B0 for ACC16)
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