Xilinx CPLD Libraries Guide

About Design Elements
Available Attributes
Attribute Type Allowed Values Default Description
DRIVE Integer 2, 4, 6, 8, 12, 16, 24 12 Specifies the output current drive
strength of the I/O. It is suggested
that you set this to the lowest setting
tolerable for the design drive and
timing requirements.
IOSTANDARD String Consult the product Data
Sheet.
"DEFAULT" Specifies the I/O standard to be used
for this output.
SLEW String "SLOW" or "FAST” "SLOW” Specifies the slew rate of the output
driver. Consult the product Data
Sheet for recommendations of the
best setting for this attribute.
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUFT: Single-ended 3-state Output Buffer
-- All devices
-- Xilinx HDL Libraries Guide, version 10.1.1
OBUFT_inst : OBUFT
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => O, -- Buffer output (connect directly to top-level port)
I => I, -- Buffer input
T => T -- 3-state enable input
);
-- End of OBUFT_inst instantiation
Verilog Instantiation Template
// OBUFT: Single-ended 3-state Output Buffer
// All devices
// Xilinx HDL Libraries Guide, version 10.1.1
OBUFT #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
) OBUFT_inst (
.O(O), // Buffer output (connect directly to top-level port)
.I(I), // Buffer input
.T(T) // 3-state enable input
);
// End of OBUFT_inst instantiation
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 507