Xilinx CPLD Libraries Guide

OBUF16
Macro: 16-Bit Output Buffer
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
This design element is a multiple output buffer.
About Design Elements
This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists in
input/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard used
by this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOW
or FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
Instantiation Yes
Inference Recommended
Coregen and wizards No
Macro support No
This design element can be used in schematics.
Available Attributes
Attribute Type Allowed Values Default Description
DRIVE Integer 2, 4, 6, 8, 12, 16, 24 12 Specifies the output current
drive strength of the I/O. It is
suggested that you set this to
the lowest setting tolerable for
the design drive and timing
requirements.
IOSTANDARD String Consult the product Data
Sheet.
"DEFAULT" Specifies the I/O standard to be
used for this output.
SLEW String "SLOW" or "FAST” "SLOW” Specifies the slew rate of
the output driver. Consult
the product Data Sheet for
recommendations of the best
setting for this attribute.
For More Information
• See the appropriate CPLD User Guide.
CPLD Libraries Guide
496 www.xilinx.com ISE 10.1