Xilinx CPLD Libraries Guide

About Design Elements
ADSU4
Macro: 4-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
When the ADD input is High, ADSU4 adds two 4-bit words (A3 – A0 and B3 – B0) and a CI are added, producing
a 4-bit sum output (S3 – S0) and CO or OFL. For this element, two 4-bit words (A3 – A0 and B3 – B0) and a CI are
added, producing a 4-bit sum output (S3 – S0) and CO or OFL
When the ADD input is Low, this element subtracts Bz – B0 from Az– A0, producing a 4-bit difference (S3 – S0)
and CO or OFL.
In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low. OFL is active-High in
add and subtract modes.
Logic Table
Input Output
ADD A B S
1 An Bn An+Bn+CI*
0 An Bn An-Bn-CI*
CI*: ADD = 0, CI, CO active LOW
CI*: ADD = 1, CI, CO active HIGH
Unsigned Binary Versus Twos Complement
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 39