Xilinx CPLD Libraries Guide

M8_1E
Macro: 8-to-1 Multiplexer with Enable
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is an 8-to-1 multiplexer with enable. When the enable input (E) is High, the M8_1E
multiplexer chooses one data bit from eight sources (D7 – D0) under the control of the select inputs (S2 – S0). The
output (O) reflects the state of the selected input as shown in the logic table. When (E) is Low, the output is Low.
Logic Table
Inputs Outputs
E S2 S1 S0 D7-D0 O
0 X X X X 0
1 0 0 0 D0 D0
1 0 0 1 D1 D1
1 0 1 0 D2 D2
1 0 1 1 D3 D3
1 1 0 0 D4 D4
1 1 0 1 D5 D5
1 1 1 0 D6 D6
1 1 1 1 D7 D7
Design Entry Method
This design element is only for use in schematics.
CPLD Libraries Guide
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