Xilinx CPLD Libraries Guide

M2_1E
Macro: 2-to-1 Multiplexer with Enable
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a 2-to-1 multiplexer with enable. When the enable input (E) is High, the M2_1E chooses
one data bit from two sources (D1 or D0) under the control of select input (S0). When Low, S0 selects D0 and
when High, S0 selects D1. When (E) is Low, the output is Low.
Logic Table
Inputs Outputs
E S0 D1 D0 O
0 X X X 0
1 0 X 1 1
1 0 X 0 0
1 1 1 X 1
1 1 0 X 0
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
446 www.xilinx.com ISE 10.1