Xilinx CPLD Libraries Guide

About Design Elements
LDG4
Macro: 4-Bit Transparent Datagate Latch
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
This design element has 4 transparent DataGate latches with a common gate enable (G). These latches are used
to gate input signals in order to decrease power dissipation during periods when activity on the input pins is
not of interest to the CPLD. The data output (Q) of the latch reflects the data (D) input while the gate enable
(G) input is Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The
data on the Q output remains unchanged as long as G remains High.
The D input(s) of the LDG must be connected to a device input pad(s) and must have no other fan-outs (must not
branch). The CPLD fitter maps the G input to the device’s DataGate Enable control pin (DGE). There must be
no more than one DataGate Enable signal in the design. The DataGate Enable signal may be driven either by
a device input pin or any on-chip logic source. The DataGate Enable signal may be reused by other ordinary
logic in the design.
This latch is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can simulate
power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
G D Q
0 0 0
0 1 1
1 X No Change
› D D
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 437