Xilinx CPLD Libraries Guide

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About Design Elements Attribute Type Allowed Values Default Description INIT INTEGER 0 or 1 0 Specifies the initial value upon power-up or the assertion of GSR for the (Q) port. For More Information • See the appropriate CPLD User Guide. • See the appropriate CPLD Data Sheets. CPLD Libraries Guide 434 www.xilinx.com ISE 10.1
About Design Elements LDG Primitive: Transparent Datagate Latch Supported Architectures This design element is supported in the following architectures only: CoolRunner-II Introduction This design element is a transparent DataGate latch used for gating input signals to decrease power dissipation. The data output (Q) of the latch reflects the data (D) input while the gate enable (G) input is Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High. The D input(s) of the LDG must be connected to a device input pad(s) and must have no other fan-outs (must not branch). The CPLD fitter maps the G input to the device’s DataGate Enable control pin (DGE). There must be no more than one DataGate Enable signal in the design. The DataGate Enable signal may be driven either by a device input pin or any on-chip logic source. The DataGate Enable signal may be reused by other ordinary logic in the design. This latch is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can simulate power-on by applying a High-level pulse on the PRLD global net. Logic Table Inputs Outputs G D Q 0 0 0 0 1 1 1 X No Change › D D Design Entry Method This design element is only for use in schematics. For More Information • See the appropriate CPLD User Guide. • See the appropriate CPLD Data Sheets. CPLD Libraries Guide ISE 10.1 www.xilinx.com 435
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ISE 10.1 CPLD Libraries Guide
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Table of Contents About this Guide.
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About this Guide This guide is part
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Design Element Description BUFE4 Ma
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Design Element Description Function
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About Design Elements For More Info
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About Design Elements B0 for ACC16)
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About Design Elements • For twos-
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About Design Elements B0 for ACC8)
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About Design Elements ADD16 Macro:
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