Xilinx CPLD Libraries Guide

About Design Elements
LDCP
Primitive: Transparent Data Latch with Asynchronous Clear and Preset
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
The design element is a transparent data latch with data (D), asynchronous clear (CLR) and preset (PRE) inputs.
When (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. When PRE is High and
(CLR) is low, it presets the data (Q) output High. (Q) reflects the data (D) input while the gate (G) input is High
and (CLR) and PRE are Low. The data on the (D) input during the High-to-Low gate transition is stored in the
latch. The data on the (Q) output remains unchanged as long as (G) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can simulate
power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
CLR PRE G D Q
1 X X X 0
0 1 X X 1
0 0 1 D D
0 0 0 X No Change
0 0 fl D D
Design Entry Method
This design element is only for use in schematics.
Available Attributes
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 433