Xilinx CPLD Libraries Guide

About Design Elements
LDC
Macro: Transparent Data Latch with Asynchronous Clear
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
This design element is a transparent data latch with asynchronous clear. When the asynchronous clear input
(CLR) is High, it overrides the other inputs and resets the data (Q) output Low. (Q) reflects the data (D) input
while the gate enable (G) input is High and (CLR) is Low. The data on the (D) input during the High-to-Low gate
transition is stored in the latch. The data on the (Q) output remains unchanged as long as (G) remains low.
This latch is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can simulate
power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
CLR G D Q
1 X X 0
0 1 D D
0 0 X No Change
0 ? D D
Design Entry Method
This design element is only for use in schematics.
Available Attributes
Attribute Type Allowed Values Default Description
INIT INTEGER 0 or 1 0 Sets the initial value
of Q output after
configuration
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 431