Xilinx CPLD Libraries Guide

LD
Primitive: Transparent Data Latch
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
LD is a transparent data latch. The data output (Q) of the latch reflects the data (D) input while the gate enable
(G) input is High. The data on the (D) input during the High-to-Low gate transition is stored in the latch. The
data on the (Q) output remains unchanged as long as (G) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can simulate
power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
G D Q
1 D D
0 X No Change
fl D D
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
426 www.xilinx.com ISE 10.1