Xilinx CPLD Libraries Guide

IOBUFE
Primitive: Bi-Directional Buffer
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a bi-directional buffer that is a composite of the IBUF and OBUFE elements. The O
output is X (unknown) when IO (input/output) is Z. You can also implement IOBUFEs as interconnections
of their component elements.
Logic Table
Inputs Bidirectional Outputs
E I IO O
0 0 Z X
0 1 Z X
1 0 0 0
1 1 1 1
Design Entry Method
This design element is only for use in schematics.
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IOBUFE: Bi-Directional Buffer
-- XC9500XL/CoolRunner-II/XPLA-3
-- Xilinx HDL Language Template, version 10.1
IOBUFE_inst : IOBUFE
port map (O => user_O,
IO => user_IO,
I => user_I,
E => user_E);
-- End of IOBUFE_inst instantiation
CPLD Libraries Guide
422 www.xilinx.com ISE 10.1