Xilinx CPLD Libraries Guide

IBUF8
Macro: 8-Bit Input Buffer
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
Input Buffers isolate the internal circuit from the signals coming into the chip. This design element is contained
in input/output blocks (IOBs) and allows the specification of the particular I/O Standard to configure the I/O. In
general, an this element should be used for all single-ended data input or bidirectional pins.
Design Entry Method
Instantiation Yes
Inference Recommended
Coregen and wizards No
Macro support No
This design element can be used in schematics.
In general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It is
generally not necessary to specify them in the source code however if desired, they be manually instantiated by
either copying the instantiation code from the ISE Libaries Guide HDL Template and paste it into the top-level
entity/module of your code. It is recommended to always put all I/O components on the top-level of the design to
help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of the design
and the O port to the logic in which this input is to source. Specify the desired generic/defparam values in
order to configure the proper behavior of the buffer.
Available Attributes
Attribute Type Allowed Values Default Description
IOSTANDARD String See Note Below DEFAULT Sets the programmable I/O
standard for the input.
IBUF_DELAY
_VALUE
IFD_DELAY
_VALUE
Binary 0 thru 12 0 Specifies the amount of
additional delay to add to
the non-registered path out of
the IOB
Binary AUTO, 0 thru 6 AUTO Specifies the amount of
additional delay to add to
the registered path within the
IOB
CPLD Libraries Guide
416 www.xilinx.com ISE 10.1