Xilinx CPLD Libraries Guide

FTP
Macro: Toggle Flip-Flop with Asynchronous Preset
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a toggle flip-flop with toggle enable and asynchronous preset. When the asynchronous
preset (PRE) input is High, all other inputs are ignored and output (Q) is set High. When toggle-enable input (T)
is High and (PRE) is Low, output (Q) toggles, or changes state, during the Low-to-High clock (C) transition.
For CPLD devices, this flip-flop is asynchronously cleared, output Low, when power is applied. You can simulate
power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
PRE T C Q
1 X X 1
0 0 X No Change
0 1 › Toggle
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
398 www.xilinx.com ISE 10.1