Xilinx CPLD Libraries Guide

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FTDRSLE About Design Elements Macro: Dual-Edge Triggered Toggle Flip-Flop with Clock Enable and Synchronous Reset and Set Supported Architectures This design element is supported in the following architectures only: CoolRunner-II Introduction This design element is a dual edge triggered toggle/loadable flip-flop with toggle and clock enable and synchronous reset and set. The synchronous reset input (R), when High, overrides all other inputs and resets the data output (Q) Low. (Reset has precedence over Set.) When R is Low and synchronous set input (S) is High, the clock enable input (CE) is overridden and output Q is set High. When R and S are Low and load enable input (L) is High, CE is overridden and data on data input (D) is loaded into the flip-flop during the Low-to-High and High-to-Low clock transitions. When R, S, and L are Low and CE is High, output Q toggles, or changes state, during the Low-to-High and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can simulate power-on by applying a High-level pulse on the PRLD global net. Logic Table Inputs Outputs R S L CE T D C Q 1 0 X X X X › 0 1 0 X X X X fl 0 0 1 X X X X › 1 0 1 X X X X fl 1 0 0 1 X X 1 › 1 0 0 1 X X 1 fl 1 0 0 1 X X 0 › 0 0 0 1 X X 0 fl 0 0 0 0 0 X X X No Change 0 0 0 1 0 X X No Change CPLD Libraries Guide 396 www.xilinx.com ISE 10.1
About Design Elements Inputs Outputs R S L CE T D C Q 0 0 0 1 1 X › Toggle 0 0 0 1 1 X fl Toggle Design Entry Method This design element is only for use in schematics. For More Information • See the appropriate CPLD User Guide. • See the appropriate CPLD Data Sheets. CPLD Libraries Guide ISE 10.1 www.xilinx.com 397
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ISE 10.1 CPLD Libraries Guide
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Table of Contents About this Guide.
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About this Guide This guide is part
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Design Element Description BUFE4 Ma
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Design Element Description Function
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About Design Elements This section
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About Design Elements For More Info
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About Design Elements B0 for ACC16)
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About Design Elements • For twos-
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About Design Elements B0 for ACC8)
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About Design Elements ADD16 Macro:
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About Design Elements Design Entry
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About Design Elements Inputs Output
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About Design Elements Logic Table I
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