Xilinx CPLD Libraries Guide

About Design Elements
FTDRSE
Macro: Dual-Edge Triggered Toggle Flip-Flop with Synchronous Reset, Set, and Clock Enable
Supported Architectures
This design element is supported in the following architectures only:
CoolRunner-II
Introduction
This design element is a dual edge triggered toggle flip-flop with toggle and clock enable and synchronous reset
and set. When the synchronous reset input (R) is High, it overrides all other inputs and the data output (Q) is
reset Low. When the synchronous set input (S) is High and R is Low, clock enable input (CE) is overridden and
output Q is set High. (Reset has precedence over Set.) When toggle enable input (T) and CE are High and R and
S are Low, output Q toggles, or changes state, during the Low-to-High and High-to-Low clock transitions.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
R S CE T C Q
1 X X X › 0
1 X X X fl 0
0 1 X X › 1
0 1 X X fl 1
0 0 0 X X No Change
0 0 1 0 X No Change
0 0 1 1 › Toggle
0 0 1 1 fl Toggle
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 395