Xilinx CPLD Libraries Guide

About Design Elements
FTC
Primitive: Toggle Flip-Flop with Asynchronous Clear
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
This design element is a synchronous, resettable toggle flip-flop. The asynchronous clear (CLR) input, when
High, overrides all other inputs and resets the data output (Q) Low. The (Q) output toggles, or changes state,
when the toggle enable (T) input is High and (CLR) is Low during the Low-to-High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
CLR T C Q
1 X X 0
0 0 X No Change
0 1 › Toggle
Design Entry Method
You can instantiate this element when targeting a CPLD, but not when you are targeting an FPGA.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 381