Xilinx CPLD Libraries Guide

About Design Elements
FJKPE
Macro: J-K Flip-Flop with Clock Enable and Asynchronous Preset
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
This design element is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous preset (PRE)
inputs and data output (Q). The asynchronous preset (PRE), when High, overrides all other inputs and sets the
(Q) output High. When (PRE) is Low and (CE) is High, the (Q) output responds to the state of the J and K
inputs, as shown in the logic table, during the Low-to-High clock (C) transition. When (CE) is Low, clock
transitions are ignored.
For CPLD devices, this flip-flop is asynchronously cleared, output Low, when power is applied. You can simulate
power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
PRE CE J K C Q
1 X X X X 1
0 0 X X X No Change
0 1 0 0 X No Change
0 1 0 1 › 0
0 1 1 0 › 1
0 1 1 1 › Toggle
Design Entry Method
This design element is only for use in schematics.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 375