Xilinx CPLD Libraries Guide

FJKCP
Macro: J-K Flip-Flop with Asynchronous Clear and Preset
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), and asynchronous preset
(PRE) inputs and data output (Q). When the asynchronous clear (CLR) is High, all other inputs are ignored and
Q is reset 0. The asynchronous preset (PRE), when High, and CLR set to Low overrides all other inputs and
sets the Q output High. When CLR and PRE are Low, Q responds to the state of the J and K inputs during the
Low-to-High clock transition, as shown in the following logic table.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
CLR PRE J K C Q
1 X X X X 0
0 1 X X X 1
0 0 0 0 X No Change
0 0 0 1 ¦ 0
0 0 1 0 ¦ 1
0 0 1 1 ¦ Toggle
Design Entry Method
This design element is only for use in schematics.
For More Information
• See the appropriate CPLD User Guide.
CPLD Libraries Guide
370 www.xilinx.com ISE 10.1