Xilinx CPLD Libraries Guide

About Design Elements
FDS
Macro: D Flip-Flop with Synchronous Set
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
FDS is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). The
synchronous set input, when High, sets the Q output High on the Low-to-High clock (C) transition. The data on
the D input is loaded into the flip-flop when S is Low during the Low-to-High clock (C) transition.
For CPLD devices, this flip-flop is asynchronously cleared, output Low, when power is applied. You can simulate
power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
S D C Q
1 X › 1
0 D › D
Design Entry Method
This design element is only for use in schematics.
Available Attributes
Attribute Type Allowed Values Default Description
INIT 1-Bit Binary 0 or 1 0 Sets the initial value of Q output after
configuration.
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 363