Xilinx CPLD Libraries Guide

Available Attributes
Attribute Type Allowed Values Default Description
About Design Elements
INIT 1-Bit Binary 0 or 1 0 Sets the initial value of Q output after configuration
and on GSR.
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
-- Clock Enable (posedge clk). All families.
-- Xilinx HDL Libraries Guide, version 10.1.1
FDRSE_inst : FDRSE
generic map (
INIT => ’0’) -- Initial value of register (’0’ or ’1’)
port map (
Q => Q, -- Data output
C => C, -- Clock input
CE => CE, -- Clock enable input
D => D, -- Data input
R => R, -- Synchronous reset input
S => S -- Synchronous set input
);
-- End of FDRSE_inst instantiation
Verilog Instantiation Template
// FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
// Clock Enable (posedge clk).
// All families.
// Xilinx HDL Libraries Guide, version 10.1.1
FDRSE #(
.INIT(1’b0) // Initial value of register (1’b0 or 1’b1)
) FDRSE_inst (
.Q(Q), // Data output
.C(C), // Clock input
.CE(CE), // Clock enable input
.D(D), // Data input
.R(R), // Synchronous reset input
.S(S) // Synchronous set input
);
// End of FDRSE_inst instantiation
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
362 www.xilinx.com ISE 10.1