Xilinx CPLD Libraries Guide

About Design Elements
FDRS
Macro: D Flip-Flop with Synchronous Reset and Set
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data
output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Low
during the Low-to-High clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, the
flip-flop is set, output High, during the Low-to-High clock transition. When R and S are Low, data on the (D)
input is loaded into the flip-flop during the Low-to-High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
R S D C Q
1 X X fl 0
0 1 X fl 1
0 0 D fl D
Design Entry Method
This design element is only for use in schematics.
Available Attributes
Attribute Type Allowed Values Default Description
INIT 1-Bit Binary 0 or 1 0 Sets the initial value of Q output after configuration.
For More Information
• See the appropriate CPLD User Guide.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 359