Xilinx CPLD Libraries Guide

FDRE
Macro: D Flip-Flop with Clock Enable and Synchronous Reset
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
About Design Elements
This design element is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs
and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q)
output Low on the Low-to-High clock (C) transition. The data on the (D) input is loaded into the flip-flop when
R is Low and CE is High during the Low-to-High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For CPLD devices, you can
simulate power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
R CE D C Q
1 X X › 0
0 0 X X No Change
0 1 D › D
Design Entry Method
This design element is only for use in schematics.
Available Attributes
Attribute Type Allowed Values Default Description
INIT 1-Bit Binary 0 or 1 0 Sets the initial value
of Q output after
configuration
For More Information
• See the appropriate CPLD User Guide.
• See the appropriate CPLD Data Sheets.
CPLD Libraries Guide
358 www.xilinx.com ISE 10.1