Xilinx CPLD Libraries Guide

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• See the appropriate CPLD Data Sheets. About Design Elements CPLD Libraries Guide 354 www.xilinx.com ISE 10.1
About Design Elements FDPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset Supported Architectures This design element is supported in the following architectures only: • XC9500XL • CoolRunner XPLA3 • CoolRunner-II Introduction This design element is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the (Q) output High. Data on the (D) input is loaded into the flip-flop when PRE is Low and CE is High on the Low-to-High clock (C) transition. When CE is Low, the clock transitions are ignored. For CPLD devices, this flip-flop is asynchronously cleared, output Low, when power is applied. You can simulate power-on by applying a High-level pulse on the PRLD global net. Logic Table Inputs Outputs PRE CE D C Q 1 X X X 1 0 0 X X No Change 0 1 D › D Design Entry Method This design element is only for use in schematics. Available Attributes Attribute Type Allowed Values Default Description INIT 1-Bit Binary 0 or 1 0 Sets the initial value of Q output after configuration CPLD Libraries Guide ISE 10.1 www.xilinx.com 355
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ISE 10.1 CPLD Libraries Guide
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Table of Contents About this Guide.
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Design Element Description BUFE4 Ma
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Design Element Description Function
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About Design Elements For More Info
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About Design Elements B0 for ACC16)
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About Design Elements B0 for ACC8)
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About Design Elements Design Entry
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