Xilinx CPLD Libraries Guide

About Design Elements
FDP
Macro: D Flip-Flop with Asynchronous Preset
Supported Architectures
This design element is supported in the following architectures only:
• XC9500XL
• CoolRunner XPLA3
• CoolRunner-II
Introduction
This design element is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data
output (Q). The asynchronous PRE, when High, overrides all other inputs and presets the (Q) output High. The
data on the (D) input is loaded into the flip-flop when PRE is Low on the Low-to-High clock (C) transition.
For CPLD devices, this flip-flop is asynchronously cleared, output Low, when power is applied. You can simulate
power-on by applying a High-level pulse on the PRLD global net.
Logic Table
Inputs Outputs
PRE C D Q
1 X X 1
0 › D D
0 › 0 0
Design Entry Method
This design element is only for use in schematics.
Available Attributes
Attribute Type Allowed Values Default Description
INIT 1-Bit Binary 0 or 1 0 Sets the initial value
of Q output after
configuration
For More Information
• See the appropriate CPLD User Guide.
CPLD Libraries Guide
ISE 10.1 www.xilinx.com 353